Process for forming a diffusion barrier using an insulating spacer layer

• US 5,770,498 A
• Filed: 01/31/1996
• Issued: 06/23/1998
• Est. Priority Date: 01/31/1996
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Becker, David S.
• Primary Examiner(s): Nguyen, Tuan H.
• Application Number:
  US08/594,794
• Time in Patent Office: 874 Days
• Field of Search: 438/230, 438/231, 438/232, 438/239, 438/250, 438/253, 438/396
• US Class Current: 438/239
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor

Abstract

An etch process that uses a single partially etched spacer insulating layer to form both sidewall spacers and a diffusion barrier that protect areas of the substrate during subsequent processing steps in the formation of semiconductor devices such as Dynamic Random Access Memories (DRAMs). The process includes the steps of: (a) forming a gate electrode over a semiconductor substrate; (b) defining first and second contact regions in the substrate adjacent sides of the gate electrode; (c) conformally depositing a spacer insulating layer over the gate electrode and the contact regions; and (d) partially etching the spacer insulating layer to remove only a portion of the thickness of the spacer insulating layer at least over the contact regions of the substrate.

Claims

1. A process for making a semiconductor device, comprising the steps of:

a. forming a gate electrode over a semiconductor substrate;

b. defining first and second contact regions in the substrate adjacent sides of the gate electrode;

c. conformally depositing a spacer insulating layer over the gate electrode and the contact regions;

d. partially etching the spacer insulating layer to remove only a portion of the thickness of the spacer insulating layer at least over the contact regions;

e. forming a lower insulating layer over the spacer insulating layer;

f. patterning and etching the lower insulating layer to form a capacitor container over the first contact region and to expose the spacer insulating layer over the first contact region; and

g. etching the exposed portion of the spacer insulating layer to expose the first contact region.

2. A process according to claim 1, wherein the spacer insulating layer is made of a material that is selectively etchable with respect to the lower insulating layer.

3. A process according to claim 2, wherein the spacer insulating layer is made of silicon nitride.

4. A process according to claim 2, further comprising the steps of:

a. forming a capacitor first conductor in the capacitor container, the first conductor being in electrical contact with the first contact region;

b. forming a capacitor dielectric layer on the capacitor first conductor; and

c. forming a capacitor second conductor on the capacitor dielectric layer.

5. A process according to claim 4, further comprising the steps of:

a. forming an upper insulating layer on the wafer;

b. patterning and etching the upper insulating layer to form an opening over the second contact region and to expose the spacer insulating layer over the second contact region;

c. etching the exposed portion of the spacer insulating layer to expose the second contact region; and

d. forming a contact in the opening, the contact being in electrical contact with the second contact region.

6. A process for making a dynamic random access memory cell, comprising the steps of:

a. providing an integrated circuit wafer having a semiconducting substrate, a plurality of transistor gate members each comprising a gate insulating layer formed on the substrate and a gate conducting layer formed on the gate insulating layer, and first and second source/drain regions on the semiconducting substrate;

b. forming a spacer insulating layer over the wafer to cover the gate members and source/drain regions;

c. partially etching the spacer insulating layer to remove a portion of the thickness of the spacer insulating layer at least over the source/drain regions;

d. forming a lower insulating layer over the spacer insulating layer;

e. patterning and etching the lower insulating layer to form a capacitor container over the first source/drain region and to expose the spacer insulating layer over the first source/drain region;

f. etching the exposed portion of the spacer insulating layer to expose the first source/drain region;

g. forming a capacitor first conductor in the capacitor container, the first conductor being in electrical contact with the first source/drain region;

h. forming a capacitor dielectric layer on the capacitor first conductor; and

i. forming a capacitor second conductor on the capacitor dielectric layer.

7. A process according to claim 6, further comprising the steps of:

a. forming an upper insulating layer on the wafer;

b. patterning and etching the upper insulating layer to form an opening over the second source/drain region and to expose the spacer insulating layer over the second source/drain region;

c. etching the exposed portion of the spacer insulating layer to expose the second source/drain region; and

d. forming a contact in the opening, the contact being in electrical contact with the second source/drain region.

8. A process according to claim 6, wherein the spacer insulating layer is made of a material that is selectively etchable with respect to oxide materials.

9. A process according to claim 6, wherein the spacer insulating layer is made of silicon nitride.

10. A process according to claim 6, wherein the spacer insulating layer is etched to a thickness in the range of 50 angstroms to 400 angstroms.

11. A process according to claim 6, wherein the spacer insulating layer is anisotropically etched to form substantially vertical spacers along sidewalls of the gate electrodes.