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Method for increasing latch-up immunity in CMOS devices

  • US 5,770,504 A
  • Filed: 03/17/1997
  • Issued: 06/23/1998
  • Est. Priority Date: 03/17/1997
  • Status: Expired due to Term
First Claim
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1. A method for reducing the damaging effects of latch-up in CMOS devices comprising the steps of:

  • a) providing a semiconductor substrate;

    b) defining a shallow trench in said semiconductor substrate; and

    c) implanting a mobility degrading species below said shallow trench, wherein said mobility degrading species comprises n-type and p-type species in combination to provide a low net dopant profile change in said semiconductor substrate.

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