Method for increasing latch-up immunity in CMOS devices

• US 5,770,504 A
• Filed: 03/17/1997
• Issued: 06/23/1998
• Est. Priority Date: 03/17/1997
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Tlan, Xiaowei, Gauthier, Robert J. Jr., Brown, Jeffrey S.
• Primary Examiner(s): Niebling, John
• Assistant Examiner(s): Pham, Long
• Application Number:
  US08/819,615
• Time in Patent Office: 463 Days
• Field of Search: 148/DIG. 85, 148/DIG. 86, 148/DIG. 50, 438/294, 438/296, 438/221, 438/222, 438/223, 438/424, 438/430, 438/433, 438/524, 438/158, 438/168, 438/172, 438/218, 438/227, 257/371, 257/374, 257/520
• US Class Current: 438/296
• CPC Class Codes: H01L 27/0921 Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
• CPC Class Codes: Y10S 148/04 Dopants, special
• CPC Class Codes: Y10S 148/05 Etch and refill
• CPC Class Codes: Y10S 148/085 Isolated-integrated
• CPC Class Codes: Y10S 148/086 Isolated zones

Abstract

The preferred embodiment of the present invention overcomes the limitations of the prior art and provides a device and method to increase the latch-up immunity of CMOS devices by reducing the mobility of carriers between the devices. The preferred embodiment uses an implant formed beneath trench isolation between n-channel and p-channel devices. This implant preferably comprises relatively large/heavy elements implanted into the wafer beneath the trench isolation. The implant elements reduce the mobility of the charge carriers. This increases the latch-up holding voltage and thus reduces the likelihood of latch-up. The implants can be formed without the need for additional photolithography masks.

Claims

1. A method for reducing the damaging effects of latch-up in CMOS devices comprising the steps of:

a) providing a semiconductor substrate;

b) defining a shallow trench in said semiconductor substrate; and

c) implanting a mobility degrading species below said shallow trench, wherein said mobility degrading species comprises n-type and p-type species in combination to provide a low net dopant profile change in said semiconductor substrate.

2. A method for reducing the damaging effects of latch-up in CMOS devices comprising the steps of:

a) providing a semiconductor substrate;

b) defining a shallow trench in said semiconductor substrate; and

c) implanting a mobility degrading species below said shallow trench, wherein said mobility degrading species comprises a neutral species to provide a low dopant profile change in said semiconductor substrate.

3. A method for reducing the damaging effects of latch-up in CMOS devices comprising the steps of:

a) providing a semiconductor substrate;

b) defining a shallow trench in said semiconductor substrate; and

c) implanting a mobility degrading species below said shallow trench, wherein said mobility degrading species comprises argon.

4. A method for reducing the damaging effects of latch-up in CMOS devices comprising the steps of:

a) providing a semiconductor substrate;

b) defining a shallow trench in said semiconductor substrate; and

c) implanting a mobility degrading species below said shallow trench, wherein said mobility degrading species comprises oxygen.

5. A method for reducing the damaging effects of latch-up in CMOS devices comprising the steps of:

a) providing a semiconductor substrate;

b) defining a shallow trench in said semiconductor substrate; and

c) implanting a mobility degrading species below said shallow trench, wherein said mobility degrading species comprises germanium.

6. A method for reducing the damaging effects of latch-up in CMOS devices comprising the steps of:

a) providing a semiconductor substrate;

b) defining a shallow trench in said semiconductor substrate; and

c) implanting a mobility degrading species below said shallow trench, wherein said mobility degrading species comprises nitrogen.

7. A method for reducing the damaging effects of latch-up in CMOS devices comprising the steps of:

a) providing a semiconductor substrate;

b) defining a shallow trench in said semiconductor substrate; and

c) implanting a mobility degrading species below said shallow trench, wherein said mobility degrading species comprises indium and antimony.

8. A method for reducing the damaging effects of latch-up in CMOS devices comprising the steps of:

a) providing a semiconductor substrate;

b) defining a shallow trench in said semiconductor substrate; and

c) implanting a mobility degrading species below said shallow trench, wherein said mobility degrading species comprises boron and phosphorus.