Method of forming lightly doped drains in metalic oxide semiconductor components

• US 5,770,508 A
• Filed: 06/04/1997
• Issued: 06/23/1998
• Est. Priority Date: 03/17/1997
• Status: Expired due to Term

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Chou, Jih-Wen, Chen, Coming, Yeh, Wen-Kuan
• Primary Examiner(s): TRINH, MICHAEL MANH
• Application Number:
  US08/868,816
• Time in Patent Office: 384 Days
• Field of Search: 438/305, 438/306, 438/307, 438/301, 438/303, 438/299, 438/174, 438/182, 438/185, 438/188, 438/199, 438/204
• US Class Current: 438/305
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66598 forming drain [D] and lightly doped drain [LDD] simultaneously, e.g. using implantation through the wings a T-shaped layer, or through a specially shaped layer
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

The present invention relates to a method of forming lightly doped drains in metallic oxide semiconductor (MOS) components. The method includes forming a first, second, and third insulating layer above a silicon substrate having a gate, etching back the layers to leave behind L-shaped first spacers on sidewalls of the gate, followed by doping second type ions into the silicon substrate to form first lightly doped drains in the silicon substrate surface below the L-shaped first spacers, and second lightly doped drains in the silicon substrate surface elsewhere, further forming a fourth insulating to form third spacers, and using the using the third spacers, the first insulating layer, and the gate as masks when doping second type ions into the silicon substrate so as to form source/drain regions in silicon substrate surfaces not covered by the third spacers. Such a method produces greater yield and reduces leakage current from the transistor components.

Claims

1. A method of forming lightly doped drains in MOS components comprising:

providing a silicon substrate doped with first type ions, a first insulating layer, and a gate;

forming a second insulating layer and a third insulating layer above the silicon substrate;

etching back the third and the second insulating layers so as to completely remove the second insulating layer above the gate while leaving behind L-shaped first spacers and second spacers on sidewalls of the gate;

removing the second spacers, followed by doping second type ions into the silicon substrate to form first lightly doped drains in the silicon substrate surface below the L-shaped first spacers, and second lightly doped drains in the silicon substrate surface elsewhere;

forming a fourth insulating layer above the silicon substrate, followed by etching back the fourth insulating layer so as to form third spacers; and

using the third spacers, the first insulating layer, and the gate as masks when doping second type ions into the silicon substrate so as to form source/drain regions in silicon substrate surfaces not covered by the third spacers.

2. A method of forming according to claim 1, wherein the first type ions are boron ions.

3. A method of forming according to claim 1, wherein the first insulating layer is a field oxide layer.

4. A method of forming according to claim 1, wherein the first insulating layer is a shallow trench isolation.

5. A method of forming according to claim 1, wherein the second insulating layer is a silicon dioxide layer.

6. A method of forming according to claim 1, wherein the thickness of the second insulating layer is between about 100 Å

to 200 Å

.

7. A method of forming according to claim 1, wherein the third insulating layer is a silicon nitride layer.

8. A method of forming according to claim 1, wherein the thickness of the third insulating layer is between about 1500 Å

to 2000 Å

.

9. A method of forming according to claim 1, wherein the second type ions are arsenic ions.

10. A method of forming according to claim 1, wherein the doping energy for the second type ions is between about 10 to 200 KeV.

11. A method of forming according to claim 1, wherein the etching back to process is performed using an anisotropic reactive ion etching method.

12. A method of forming according to claim 1, wherein the second spacers are removed by a wet etching method using hot phosphoric acid solution.

13. A method of forming according to claim 1, wherein the first lightly doped drain is a shallow source/drain extension region.

14. A method of forming according to claim 1, wherein the second lightly doped drain is a moderate source/drain extension region.

15. A method of forming according to claim 1, wherein the fourth insulating layer is a silicon dioxide layer.

16. A method of forming according to claim 15, wherein the thickness of the silicon dioxide layer is between about 1500 Å

to 2500 Å

.

17. A method of forming according to claim 1, wherein the fourth insulating layer is a silicon nitride layer.

18. A method of forming according to claim 17, wherein the thickness of the silicon nitride layer is between about 2000 Å

to 2500 Å

.