Planar, hermetic metal matrix housing
First Claim
1. A hermetically sealable housing adapted for holding at least one semiconductor chip, and for providing electrically conductive paths from the exterior of said housing to the interior thereof, said housing comprising:
- a base member defining a bottom surface, and also defining a lower mesa, an intermediate mesa overlying said lower mesa, and an upper mesa overlying said intermediate mesa, said upper mesa defining a substantially planar top surface and a periphery, an upper portion of said lower mesa defining at least an insert bearing surface being substantially parallel with said top surface, said base member including at least one cavity extending from said top surface of said upper mesa toward said bottom surface, and adapted for holding a semiconductor chip with the upper surface of said chip substantially coplanar with said top surface of said upper mesa, said intermediate mesa and said upper mesa of said base member further including at least one flat end wall perpendicular to said top surface, and extending from said top surface of said upper mesa to said insert bearing surface over a selected portion of said periphery of said upper mesa, said intermediate mesa defining a substantially planar ring support surface lying parallel with said top surface of said upper mesa, and extending about said periphery of said upper mesa except along said selected portion of said periphery of said upper mesa;
a substantially rectilinear insert having a monolithic stepped body defining a lower surface, and including at least first and second portions, said first portion of said insert defining an upper surface and a flat contact wall having a length dimension substantially equal to the length of said selected portion of said periphery and a height dimension between said upper surface of said first portion of said insert and said lower surface of said insert, said height dimension being equal to the dimension of said flat end wall of said base member from said top surface of said base member to said insert bearing surface of said base member, said second portion of said stepped body of said insert defining at least one upper surface including terminal and non-terminal portions, and also defining a height between said lower surface of said insert and said upper surface of said terminal portion of said second portion of said insert, said height being equal to the distance between said insert bearing surface and said ring support surface of said base member, said insert being made from a dielectric material, and further including a plurality of electrical conductors extending within said dielectric material from said upper surface of said first portion of said insert to said upper surface of said terminal portion of said second portion of said insert, but not to said upper surface of said non-terminal portion of said second portion of said insert, said electrical conductors being insulated except at said upper surface of said first portion of said insert and at said upper surface of said terminal portion of said second portion of said insert, said insert being mounted with said contact wall contiguous with said end wall of said base member, and with said lower surface of said insert contiguous with said insert bearing surface of said base member, whereby said upper surface of said first portion of said insert is substantially coplanar with said top surface of said upper mesa of said base member, and said upper surface of said non-terminal portion of said second portion of said insert is substantially coplanar with said ring support surface of said base member over said selected portion of said periphery, said base member being hermetically sealed to said insert at least along said lower surface of said insert and said contact wall of said first portion of said insert; and
a peripheral sealing ring extending over said ring support surface of said base member and said top surface of said insert, to form a continuous flat surface about said periphery of said upper mesa, said sealing ring being hermetically joined to said ring support surface of said base member and to said upper surface of said nonterminal portion of said second portion of said insert.
1 Assignment
0 Petitions
Accused Products
Abstract
A hermetically sealed housing for plural GaAs chips includes a body made from Al/SiC. The body defines a peripheral seal ring support surface, an electrical connector insert support surface and an end wall to which a ceramic insert is mounted. The insert includes a first portion with an upper surface within the sealed housing, Which upper surface is coplanar with the upper surface of the body, for convenient HDI film connections to the chips and electrical connector inserts. The refractory electrical conductors extend from the upper surface of the first portion of the insert to an exterior terminal portion of the insert. The terminal portion of the insert is spaced from the first portion of the insert by a non-terminal portion containing no terminals. The non-terminal portion of the insert is coplanar with the seal ring support surface of the body, and contiguous therewith. The insert, a titanium seal ring, and the body are hermetically joined by aluminum, which fills the pores of the body and the interstices between the body, the insert, and the seal ring. A domed lid is sealed to the seal ring.
9 Citations
9 Claims
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1. A hermetically sealable housing adapted for holding at least one semiconductor chip, and for providing electrically conductive paths from the exterior of said housing to the interior thereof, said housing comprising:
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a base member defining a bottom surface, and also defining a lower mesa, an intermediate mesa overlying said lower mesa, and an upper mesa overlying said intermediate mesa, said upper mesa defining a substantially planar top surface and a periphery, an upper portion of said lower mesa defining at least an insert bearing surface being substantially parallel with said top surface, said base member including at least one cavity extending from said top surface of said upper mesa toward said bottom surface, and adapted for holding a semiconductor chip with the upper surface of said chip substantially coplanar with said top surface of said upper mesa, said intermediate mesa and said upper mesa of said base member further including at least one flat end wall perpendicular to said top surface, and extending from said top surface of said upper mesa to said insert bearing surface over a selected portion of said periphery of said upper mesa, said intermediate mesa defining a substantially planar ring support surface lying parallel with said top surface of said upper mesa, and extending about said periphery of said upper mesa except along said selected portion of said periphery of said upper mesa; a substantially rectilinear insert having a monolithic stepped body defining a lower surface, and including at least first and second portions, said first portion of said insert defining an upper surface and a flat contact wall having a length dimension substantially equal to the length of said selected portion of said periphery and a height dimension between said upper surface of said first portion of said insert and said lower surface of said insert, said height dimension being equal to the dimension of said flat end wall of said base member from said top surface of said base member to said insert bearing surface of said base member, said second portion of said stepped body of said insert defining at least one upper surface including terminal and non-terminal portions, and also defining a height between said lower surface of said insert and said upper surface of said terminal portion of said second portion of said insert, said height being equal to the distance between said insert bearing surface and said ring support surface of said base member, said insert being made from a dielectric material, and further including a plurality of electrical conductors extending within said dielectric material from said upper surface of said first portion of said insert to said upper surface of said terminal portion of said second portion of said insert, but not to said upper surface of said non-terminal portion of said second portion of said insert, said electrical conductors being insulated except at said upper surface of said first portion of said insert and at said upper surface of said terminal portion of said second portion of said insert, said insert being mounted with said contact wall contiguous with said end wall of said base member, and with said lower surface of said insert contiguous with said insert bearing surface of said base member, whereby said upper surface of said first portion of said insert is substantially coplanar with said top surface of said upper mesa of said base member, and said upper surface of said non-terminal portion of said second portion of said insert is substantially coplanar with said ring support surface of said base member over said selected portion of said periphery, said base member being hermetically sealed to said insert at least along said lower surface of said insert and said contact wall of said first portion of said insert; and a peripheral sealing ring extending over said ring support surface of said base member and said top surface of said insert, to form a continuous flat surface about said periphery of said upper mesa, said sealing ring being hermetically joined to said ring support surface of said base member and to said upper surface of said nonterminal portion of said second portion of said insert. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A hermetically sealable housing adapted for holding at least one GaAs semiconductor chip, and for providing electrically conductive paths from the exterior of said housing to the interior thereof, said housing comprising:
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a base member, made principally from AlSiC, said base member defining a bottom surface, and also defining a lower mesa, an intermediate mesa overlying said lower mesa, and an upper mesa overlying said intermediate mesa, said upper mesa defining a substantially planar top surface and a periphery, an upper portion of said lower mesa defining at least an insert bearing surface lying substantially parallel with said top surface of said upper mesa, said base member including at least one cavity extending from said top surface of said upper mesa toward said bottom surface, and adapted for holding a GaAs semiconductor chip with the upper surface of said GaAs semiconductor chip substantially coplanar with said top surface of said upper mesa, said intermediate mesa and said upper mesa of said base member including at least one flat end wall perpendicular to said top surface, and extending from said top surface of said upper mesa to said insert bearing surface over a selected portion of said periphery of said upper mesa, said intermediate mesa defining a substantially planar ring support surface lying parallel with said top surface of said upper mesa, and extending about said periphery of said upper mesa except along said selected portion of said periphery of said upper mesa; a substantially rectilinear ceramic insert having a monolithic stepped body defining a lower surface, and including at least first and second portions, said first portion of said insert defining an upper surface and a flat contact wall having a length dimension substantially equal to the length of said selected portion of said periphery and a height dimension between said upper surface of said first portion of said insert and said lower surface of said insert, said height dimension being equal to the dimension of said flat end wall of said base member from said top surface of said base member to said insert bearing surface of said base member, whereby said first portion of said insert fits to said selected portion of said periphery, said second portion of said stepped body of said insert defining at least terminal and non-terminal portions, each of said terminal and non-terminal portions having an upper surface, and also defining a height between said lower surface of said insert and said upper surface of said non-terminal portion of said second portion of said insert, said height being equal to the distance between said insert bearing surface of said lower mesa and said ring support surface of said base member, said insert further including a plurality of electrical conductors made from refractory material extending within a dielectric material from said upper surface of said first portion of said insert to said upper surface of said terminal portion of said second portion of said insert, but not to said upper surface of said non terminal portion of said second portion of said insert, said electrical conductors being insulated except at said upper surface of said first portion of said insert and at said upper surface of said terminal portion of said second portion of said insert, said insert being mounted to said base member, with said contact wall of said insert contiguous with said end wall of said base member, and with said lower surface of said insert contiguous with said insert bearing surface of said base member, whereby said upper surface of said first portion of said insert is substantially coplanar with said top surface of said base member, and said upper surface of said non-terminal portion of said second portion of said insert is substantially coplanar with said ring support surface of said base member over said selected portion of said periphery, said base member being hermetically joined by aluminum to said insert at least along said lower surface of said insert and said contact wall of said first portion of said insert; a titanium peripheral sealing ring extending over said ring support surface of said base member and said top surface of said insert, to form a continuous flat surface about said periphery of said upper mesa, said sealing ring being hermetically joined to said ring support surface of said base member and to said upper surface of said nonterminal portion of said second portion of said insert; and a lid hermetically joined to said sealing ring, to thereby hermetically seal said GaAs chip into said housing.
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Specification