Trench MOS gate device

• US 5,770,878 A
• Filed: 04/10/1996
• Issued: 06/23/1998
• Est. Priority Date: 04/10/1996
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Harris Corporation (L3Harris Technologies, Inc.)
• Inventors: Beasom, James Douglas
• Primary Examiner(s): Crane, Sara W.
• Assistant Examiner(s): CAO, PHAT X
• Application Number:
  US08/636,904
• Time in Patent Office: 804 Days
• Field of Search: 257/331, 257/517, 257/330, 257/333, 257/332, 257/341, 257/513
• US Class Current: 257/330
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 21/28211 in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer H01L21/28194 and H01L21/28202 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/511 with a compositional variation, e.g. multilayer structures H01L29/516 takes precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

The present invention is directed to an improved trench MOS gate device that comprises a trench whose floor and sidewalls include layers of dielectric material, the layers each having a controlled thickness dimension. These thickness dimensions are related by a controlled floor to sidewall layer thickness ratio, which is established by individually controlling the thickness of each of the floor and sidewall dielectric layers. This floor to sidewall layer thickness ratio is preferably at least 1 to 1, more preferably at least 1.2 to 1. Further in accordance with the present invention, a process for forming an improved trench MOS gate device comprises etching a trench in a silicon device wafer and forming layers of dielectric material on the trench floor and on the sidewalls, each layer having a controlled thickness dimension. The thickness dimensions are related by a controlled floor to sidewall layer thickness ratio that is preferably at least 1 to 1. When silicon dioxide is employed as the dielectric material, the layers preferably comprise a composite of thermally grown and deposited silicon dioxide. The trench containing the dielectric layers is filled with polysilicon, and an insulator layer is formed over the polysilicon, thereby forming a trench gate. A patterned electrically conducting metallic interconnect is formed over the trench gate.

Claims

1. An improved trench MOS gate device comprising:

a trench gate having a floor and sidewalls, said floor and said sidewalls comprising a layer of a dielectric material, said floor layer and said sidewall layers each having a substantially uniform controlled thickness dimension,

wherein said substantially uniform thickness dimensions are related by a controlled floor to sidewall layer thickness ratio, said ratio being established by individually controlling the substantially uniform thickness of each of said floor and sidewall layers, and said thickness of said floor is greater than said thickness of said sidewall layers, wherein said floor layer and said sidewall layers each comprise a composite of thermally oxidized dielectric material having an oxygen concentration that decreases in a direction toward the floor or sidewall and deposited dielectric material having a substantially constant oxygen concentration.

2. A trench MOS gate device according to claim 1, wherein said dielectric material comprises silicon dioxide.

3. A trench MOS gate device according to claim 1, wherein said thickness ratio is at least 1.2 to 1.

4. A trench MOS gate device according to claim 2, wherein said floor layer comprises silicon dioxide with a thickness of 300 to 3,000 angstroms.

5. A trench MOS gate device according to claim 2, wherein said sidewall layers comprise silicon dioxide with a thickness of 200 to 1,500 angstroms.

6. A trench MOS gate device according to claim 1, wherein said trench gate further comprises doped polysilicon disposed within said trench.

7. A trench MOS gate device according to claim 1, wherein said trench has an open-cell, stripe topology.

8. A trench MOS gate device according to claim 1, wherein said trench has a closed-cell, cellular topology.

9. A trench MOS gate device according to claim 8, wherein said trench has a square cellular topology.

10. A trench MOS gate device according to claim 8, wherein said trench has a hexagonal cellular topology.

11. A semiconductor device comprising the trench MOS gate device of claim 1.

12. A semiconductor device of claim 11 comprising a DMOS transistor.

13. A semiconductor device of claim 11 comprising an insulated gate bipolar transistor.

14. A semiconductor device of claim 11 comprising an MOS-controlled thyristor.

15. A trench MOS gate device according to claim 2, wherein said thermally grown silicon dioxide comprises a product of reaction of silicon in an oxygen-containing atmosphere.

16. A trench MOS gate device according to claim 2, wherein said deposited silicon dioxide comprises a chemical vapor deposited reaction product of a volatile silicon-containing compound.