SOI FET design to reduce transient bipolar current
First Claim
1. A silicon-on-insulator field effect transistor having respective source and drain regions formed in a silicon layer over an insulator layer, said transistor includinga gap between one of said source and drain regions and said insulator layer, said gap being of a width equal to or less than a thickness of a depletion region at approximately zero volts bias between said one of said source and drain regions and said silicon layer.
1 Assignment
0 Petitions
Accused Products
Abstract
Producing a gap between a source and/or drain region of a silicon-on-insulator (SOI) field effect transistor which is less than the thickness of a depletion region normally surrounding the source and/or drain region, preferably at zero volts bias, permits gain of a parasitic bipolar transistor formed therewith to be transiently reduced and the effective base-emitter junction capacitance to be transiently increased during only modes of operation in which the parasitic bipolar conduction dominates normal operation of the field effect transistor. Such transient reduction of gain coupled with a transient reduction of high frequency response reduces the parasitic bipolar current spike to a degree greater than previously achievable and is fully compatible with other techniques of reducing such current spike. As applied to an SOICMOS SRAM, the transistor structure including such a gap is effective in suppressing half-select write disturb effects while maintaining the benefits of excess charge storage and floating body effects in the transistor.
286 Citations
21 Claims
-
1. A silicon-on-insulator field effect transistor having respective source and drain regions formed in a silicon layer over an insulator layer, said transistor including
a gap between one of said source and drain regions and said insulator layer, said gap being of a width equal to or less than a thickness of a depletion region at approximately zero volts bias between said one of said source and drain regions and said silicon layer.
-
7. A digital logic circuit including a silicon-on-insulator field effect transistor, said transistor having respective source and drain regions formed in a silicon layer over an insulator layer, said transistor including
a gap between one of said source and drain regions and said insulator layer, said gap being of a width equal to or less than a thickness of a depletion region at approximately zero volts bias between said one of said source and drain regions and said silicon layer.
-
15. A method of operating a silicon-on-insulator field effect transistor including the steps of causing a depletion region to fill a gap between one of
a source region and a drain region of said silicon-on-insulator field effect transistor and an insulator layer below said field effect transistor, and transiently reducing thickness of said depletion region to a thickness less than said gap.
Specification