Apparatus for compressing data using a Lempel-Ziv-type algorithm

• US 5,771,010 A
• Filed: 03/22/1995
• Issued: 06/23/1998
• Est. Priority Date: 03/22/1995
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Masenas, Charles J.
• Primary Examiner(s): Gaffin, Jeffrey A.
• Assistant Examiner(s): Huynh, Thuy-Trang N.
• Application Number:
  US08/408,577
• Time in Patent Office: 1,189 Days
• Field of Search: 341/51, 341/106
• US Class Current: 341/51
• CPC Class Codes: G06T 9/005 Statistical coding, e.g. Huffman, run length coding
• CPC Class Codes: H03M 7/3086 employing a sliding window, e.g. LZ77

Abstract

A data processing system having a compression and decompression apparatus based on the Lempel-Ziv algorithm. The compression apparatus includes an array section having a circular history CAM unit for receiving and storing one or more data elements and a coding unit for determining whether received data elements previously have been stored in the history CAM unit and are a candidate for compression. If a received data element matches at least one of the stored data elements, a PS logic section determines whether there is the presence of a string. An encoding section identifies the address of the matching stored data element in a string and the length of the string. The compression apparatus generates a compression token comprising an identification of whether a data element is compressed, the length of the coded data within a plurality of predetermined data length categories and an address. The compression apparatus uses a particular hardware implementation of the PS logic section.

Claims

1. A data compression apparatus for identifying repeated data element strings in a data stream having a plurality of data elements comprising:

a history buffer for concurrently storing a plurality of the data elements in separately addressable locations, each data element being stored at an addressable location;

an input means for inputting a current data element;

a plurality of comparison means each for comparing said current data element with the content of a stored data element then stored in a corresponding addressable location in said history buffer, said plurality of comparison means being operative to generate an output identifying all existing matches between said current data element and all stored data elements;

a plurality of logic means, each for receiving the corresponding output of one of said comparison means and for generating a signal identifying the existence of a strings of at least two data elements, and

an encoder responsive to said signals from said plurality of logic means for generating a first output comprising an address identifying a repeated data element string and a second output indicating the existence of a repeated data element string within said history buffer;

wherein each of said logic means comprises a means responsive to said comparison means output and the output from another logic means for generating a match signal, the match signals from each said plurality of logic means being provided to said encoder and

wherein said responsive means is further responsive to said second output of said encoder.

2. A data compression apparatus for identifying repeated data element strings in a data stream having a plurality of data elements comprising:

a history buffer for concurrently storing a plurality of the data elements in separately addressable locations, each data element being stored at an addressable location;

an input means for inputting a current data element;

a plurality of comparison means, each for comparing said current data element with the content of a stored data element then stored in a corresponding addressable location in said history buffer, said plurality of comparison means being operative to generate an output identifying all existing matches between said current data element and all stored data elements;

a plurality of logic means each for receiving the corresponding output of one of said comparison means and for generating a signal identifying the existence of a string of at least two data elements; and

an encoder responsive to said signals from said plurality of logic means for generating a first output comprising an address identifying a repeated data element string and a second output indicating the existence of a repeated data element string within said history buffer;

wherein each said logic means further comprises a binary signal generator responsive to a match signal and said comparison means output for generating a string indicator signal, and

wherein said encoder comprises means responsive to a plurality of said match signals to generate an ORed signal output indicating the existence of at least one string of matches between a current data element and said stored data elements.

3. The data compression apparatus as set forth in claim 2 wherein said binary signal generator is responsive to said Ored signal to provide an indication of a continuing string.

4. The data compression apparatus as set forth in claim 3 further comprising a register for storing said output of said binary signal generator for access by another logic means.

5. The data compression apparatus as set forth in claim 2 wherein said data compression apparatus is operative in accordance with predetermined cycles and wherein, during one cycle, a current data element is input, a comparison by all said plurality of comparison means is conducted, and said encoder generates an address and said Ored signal.

6. The data compression apparatus as set forth in claim 5 wherein said register delays said signal by one cycle.

7. A data compression apparatus for identifying repeated data element strings in a data stream having a plurality of data elements, said apparatus having a pipeline configuration comprising at least a first path and a second path, the processing of a data element in each of said first and second paths requiring an equal number of processing cycles and joining at an end thereof with a common third path, said first path comprising a CAM macro means and a means responsive to said CAM macro means for generating length and address information, said second path comprising a plurality of registers connected for forwarding a data element and providing an associated cycle delay, and said third path being responsive to outputs from said first and second paths for generating an encoded output for transmission, wherein said CAM macro means comprises at least a CAM data register means requiring a first processing cycle, a CAM match latch means responsive to said CAM data register means output and requiring a second processing cycle, and a CAM priority encode means requiring a third processing cycle, said CAM macro means further comprising a CAM register means for receiving the output of said CAM match latch means and for providing an output to said CAM priority encode means, said CAM register means requiring no processing cycle delay.

8. The data compression apparatus as set forth in claim 7 wherein said CAM macro means further comprises:

a history buffer for concurrently storing a plurality of the data elements in separately addressable locations, each data element being stored at an addressable location; and

CAM cell addressing means for addressing a location in said history buffer.

9. The data compression apparatus as set forth in claim 7 wherein said third path comprises a barrel shifter logic means for receiving said length and address information from said first path and a data element from said second path.