Graphics computer

• US 5,771,047 A
• Filed: 12/14/1994
• Issued: 06/23/1998
• Est. Priority Date: 12/17/1993
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Watabe, Mitsuru, Katsura, Koyo, Ohba, Mamoru, Minami, Rika
• Primary Examiner(s): Jankus, Almis R.
• Application Number:
  US08/355,517
• Time in Patent Office: 1,287 Days
• Field of Search: 395/143, 395/166, 395/164, 395/140-142, 395/133, 395/344, 395/443, 382/283, 382/199
• US Class Current: 345/443
• CPC Class Codes: G06T 11/203 Drawing of straight lines or curves

Abstract

To reduce the hardware of the graphics computer in size and reduce the cost of the hardware, the frame buffer and the main memory are united into one unit to process graphics data in the CPU. The frame buffer is arranged in the main memory, and the graphics computer includes a DMAC used to read pixel data from the frame buffer for display, a display used to receive the pixel data and display it on a display device, such as an LCD, etc., and memories used to store the procedure used by the CPU to draw the pixel data in the said frame buffer. Especially, the said memories are formed so that a single function procedure and a multifunction procedure can be selected to suit the drawing object. In addition, the single function procedure includes a line drawing procedure that uses data tables and a multivalue expansion procedure that uses a pattern table and a mask table. Since the frame buffer and the main memory are united into one unit, the CPU can be used to process graphics data. Thus, the graphics computer hardware is reduced in size and the cost of the hardware is reduced.

Claims

1. A microcomputer comprising:

a CPU that computes data to be displayed on a raster scanning type display unit;

a 1st address bus connected to said CPU for carrying addresses to specify a destination of said data;

a 2nd address bus connected to a memory used to store said data;

registers used to store address conversion data set by said CPU; and

an address converter that converts addresses received from the 1st address bus and outputs them to the 2nd address bus in accordance with the address conversion data set by said CPU.

2. The microcomputer described in claim 1, wherein the said address converter is provided with 1st information that specifies an area in said memory to convert addresses according to address conversion information stored in said registers, and includes means for converting addresses generated on the 1st address bus according to said 1st information.

3. The microcomputer described in claim 2, wherein said address converter is provided with 2nd information used to obtain a 1st field of a XS bit from a lower part of an address according to address conversion information stored in said registers and 3rd information used to distinguish a 2nd field of a YS bit from a 3rd field, and includes means for exchanging the 2nd and 3rd fields to convert addresses.

4. The microcomputer described in claim 3, wherein said means in said address converter for exchanging the 2nd and 3rd fields operates on an address generated on the said 1st address bus according to said 1st information.

5. The microcomputer described in claim 1, wherein said address converter is provided with 2nd information used to obtain a 1st field of a XS bit from a lower part of an address according to address conversion information stored in said registers and 3rd information used to distinguish a 2nd field of a YS bit from a 3rd field, and includes means for exchanging the 2nd and 3rd fields to convert addresses.

6. A line drawing system comprising:

a draw method control unit that generates information to select a draw method from an absolute value of a difference between start and end coordinates of a subject line to generate input information using a selected draw method;

a data storage used to store vector data therein at an address of the absolute value of the difference between the start and end coordinates;

a line coordinate generation unit that generates equations and constants to generate a line from the start and end coordinates; and

a draw unit that draws a fixed area for data received from said data storage.

7. The line drawing system described in claim 6, provided with first dedicated instructions used to select and start up said data storage and said line coordinate generation unit, and second dedicated instructions used to start up said data storage and said line coordinate generation unit without selection thereof.

8. The line drawing system described in claim 6, which is further provided with a frame memory and a display device.

9. A line drawing unit, comprising means for fixing the line processing time for up to a specific number of pixels, and means responsive to said specific number of pixels being exceeded, for setting the line processing time to a value proportional to the number of pixels which have been processed.

10. A line draw method comprising the steps of:

selecting a system to read vector data stored beforehand to generate vector data using start and end coordinates of a subject line, and selecting a system to generate equations and constants necessary to generate the subject line using the start and end coordinates to draw a fixed area of previously stored vector data.

11. A graphics computer comprising:

an extract unit that reads binary data of plural pixels;

a multivalue pattern storage that holds multivalue patterns, each of which comprises plural multivalue data for one pixel; and

a select unit that selects multivalue data, corresponding to the binary data for plural pixels read from said extract unit, from said multivalue pattern storage.

12. The graphics computer described in claim 11, which further comprises a boundary judgment unit that judges the position to start writing of pixel data according to an address of pixel data to be written in a frame buffer;

and a write execution unit that writes pixel data in the frame buffer according to said start position for writing.

13. A graphics computer comprising:

an extract unit that reads binary data of plural pixels;

a mask pattern storage that holds mask patterns to mask specified pixel data for plural pixels;

a select unit that selects a specified mask pattern from said mask patterns to process the specified pixel data for plural pixels read by said extract unit; and

a mask processing unit that executes a mask processing according to the selected mask pattern.

14. The graphics computer described in claim 13, which further comprises a boundary judgment unit that judges the position to start writing of pixel data according to an address of the pixel data to be written in a frame buffer.

15. A graphics computer comprising:

a boundary judgment unit that judges a position to start writing pixel data according to an address of pixel data to be written in a frame buffer; and

a write unit that writes pixel data in the frame buffer according to said start position for writing.

16. A graphics computer comprising:

a memory that holds binary pixel data;

an extract unit that reads binary data for plural pixels;

a multivalue pattern storage that holds multivalue patterns, each of which comprises plural multivalue data for one pixel;

a select unit that selects multivalue data from said multivalue pattern storage corresponding to binary data for plural pixels read by said extract unit; and

a display that displays pixel data received from said memory.

17. The graphics computer described in claim 16, further provided with a boundary judgment unit that judges a position to start writing pixel data according to an address of pixel data to be written in said memory, and wherein said select unit is controlled according to a result of a judgment made by the boundary judgment unit.

18. A graphics computer having a graphics processor and a display, said graphics processor comprising:

a memory that holds binary pixel data;

an extract unit that reads binary data for plural pixels;

a mask pattern storage that holds mask patterns used to mask specified pixel data for plural pixels;

a select unit that selects a specified mask pattern from said mask patterns to process specified pixel data for plural pixels read by said extract unit;

a mask processing unit that executes a mask processing using said selected mask pattern; and

a write control unit that writes the processed pixel data in the said memory; and

wherein

said display displays pixel data output from said memory.

19. The graphics computer described in claim 18, wherein said graphics processor is further provided with a boundary judgment unit that judges a position to start writing of pixel data according to an address of pixel data to be written in said memory, and wherein said select unit is controlled according to a result output from said judgment unit.

20. A microcomputer comprising:

a CPU that computes data to be displayed on a raster scanning-type display unit, said CPU being equipped with;

an extract unit that reads binary data of plural pixels,

a multi value pattern storage means for holding multi value patterns, each of which includes plural multi value data for one pixel, and

a select unit that selects multi value data, corresponding to the binary data from plural pixels read from said extract unit, from said multi value pattern storage;

a first address bus connected to said CPU for carrying addresses to specify a destination of said data;

a second address bus connected to a memory used to store said data;

a plurality of registers for storing address conversion data set by said CPU; and

an address converter for converting addresses received from the first address bus and outputting them to the second address bus.

21. A microcomputer comprising:

a CPU that computes data to be displayed on a raster scanning-type display unit, said CPU being equipped with;

a draw method control unit for generating information to select a draw method from an absolute value of a difference between start and end coordinates of a subject line to generate input information using a selected draw method,

a data storage means for storing vector data at a address corresponding to the absolute value of a difference between the start and end coordinates,

a line coordinate generation unit for generating equations and constance to generate a line from the start and end coordinates, and

a draw unit for drawing a fixed area for data received from said data storage;

a first address bus connected to said CPU for carrying addresses to specify a destination of said data;

a second address bus connected to a memory for storing said data;

a plurality of registers for storing store address conversion data set by said CPU; and

an address converter for converting addresses received from the first address bus and outputting them to the second address bus.

22. A microcomputer comprising:

a CPU for computing data to be displayed on a raster scanning-type display unit, said CPU being equipped with a line drawing unit comprising;

means for fixing a line processing time for up to a specific number of pixels, and

means responsive to said specific number of pixels being exceeded, for setting the line processing time to a value proportional to the number of pixels which have been processed;

a first address bus connected to said CPU for carrying addresses to specify a destination of said data;

a second address bus connected to a memory used to store said data;

registers for storing address conversion data set by said CPU; and

an address converter for converting addresses received from the first address bus and outputting them to the second address bus.

23. A microcomputer comprising:

a CPU for computing data to be displayed on a raster scanning-type display unit, said CPU being equipped with a graphics computing unit comprising;

an extract unit for reading binary data of plural pixels,

a multi value pattern storage means for holding multi value patterns, each of which comprises plural multi value data for one pixel,

a select unit for selecting multi value data, corresponding to binary data for plural pixels read from said extract unit, from said multi value pattern storage, and

a boundary judgement unit for judging the position to start writing of pixel data according to an address of pixel data to be written in a frame buffer, and

a write execution unit for writing pixel data in the frame buffer according to said start position for writing;

a first address bus connected to said CPU for carrying addresses to specify a destination of said data;

a second address bus connected to a memory for storing said data;

a plurality of registers for storing address conversion data set by said CPU; and

an address converter for converting addresses received from the first address bus and outputting them to the second address bus.

24. A microcomputer comprising:

a CPU that computes data to be displayed on a raster scanning type display unit;

a first address bus connected to said CPU for carrying addresses to specify a destination of said data;

a second address bus connected to a memory used to store said data;

a register used to store address conversion information specifying an address conversion mode set by said CPU; and

an address converter that converts addresses received from the first address bus and outputs them to the second address bus in accordance with the address conversion mode set by said CPU, wherein the address conversion mode is executed such that said addresses are arranged sequentially in two-dimensions in a plurality of blocks having a smaller area than the display, and wherein a size of each of said plurality of blocks is determined by said register.

25. The microcomputer described in claim 24, wherein said address converter is provided with first information that specifies an area in said memory to convert addresses according to address conversion information stored in said register, and includes means for converting addresses generated on the first address bus according to said first information.

26. The microcomputer described in claim 25, wherein said address converter is provided with second information used to obtain a first field of a XS bit from a lower part of an address according to address conversion information stored in said register and third information used to distinguish a second field of a YS bit from a third field, and includes means for exchanging the second and third fields to convert addresses.

27. The microcomputer described in claim 26, wherein said means in said address converter for exchanging the second and third fields operates on an address generated on said first address bus according to said first information.

28. The microcomputer described in claim 24, wherein said address converter is provided with second information used to obtain a 1st field of a XS bit from a lower part of an address according to address conversion information stored in said register and third information used to distinguish a second field of a YS bit from a third field, and includes means for exchanging the second and third fields to convert addresses.