Multiple level storage DRAM cell

• US 5,771,187 A
• Filed: 12/23/1996
• Issued: 06/23/1998
• Est. Priority Date: 12/23/1996
• Status: Expired due to Term

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Kapoor, Ashok
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): TRAN, MICHAEL THANH
• Application Number:
  US08/779,994
• Time in Patent Office: 547 Days
• Field of Search: 365/149
• US Class Current: 365/149
• CPC Class Codes: G11C 11/565 using capacitive charge storage elements
• CPC Class Codes: G11C 7/16 Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters

Abstract

A semiconductor memory device which includes a word line, a bit line and a storage capacitor having first and second ends. A pair of FEATS each having gates coupled to the word line and one side coupled to the bit line. The other side of each FEAT is coupled to a storage capacitor upon which a selected one of four potential levels, corresponding to stored values of zero, one, two, or three, can be stored and thereafter read. One of the FEATS has a thicker gate oxide than the other and thus a higher threshold voltage. Voltage stored on the capacitor is read in two cycles thereby producing in the first cycle a high level pulse, a low level pulse, or no pulse and in the second cycle, a low level pulse or no pulse, depending upon the level of charge stored on the capacitor.

Claims

1. A semiconductor memory device having a word line and a bit line, said semiconductor memory device comprising:

a storage capacitor having first and second ends;

a first transistor having a gate coupled to said word line, a first terminal coupled to said bit line and a second terminal coupled to said first end of said storage capacitor;

a second transistor having a gate coupled to said word line, a first terminal coupled to said bit line and a second terminal coupled to said first end of said storage capacitor, and

a circuit coupled to said bit line, said circuit being operable to apply a selected one of at least three potential levels to said bit line for storing said selected level on said capacitor when at least one of said transistors is conducting.

2. The memory device of claim 1 wherein said first and second transistors have different threshold voltages.

4. The memory device of claim 1 wherein said capacitor comprises a trench capacitor.

5. The memory device of claim 1 wherein said second end of said capacitor is coupled to a ground potential.

3. The memory device of claim I wherein said first and second transistors each include a layer of gate oxide, said layers having substantially! different thicknesses.

6. The memory device of claim I wherein one of said transistors conducts a larger amount of charge than the other transistor when both are substantially turned on.

7. A method of reading a selected one of at least three potential levels stored on a storage capacitor in a semiconductor memory device having a word line and a bit line, said method comprising:

applying said selected one of at least three potential levels to said bit line to store said selected potential level on said storage capacitor,

coupling the potential on said storage capacitor to said bit line for a first gating period having a first predetermined duration;

conducting a first portion of any charge on said storage capacitor to said bit line,

sensing a first bit line the! potential on said bit line resulting from such coupling!;

coupling the potential on said storage capacitor to said bit line for a second gating) period having a second predetermined duration;

conducting a second portion of any remaining charge on said storage capacitor to said bit line; and

sensing a second bit line potential on said bit line.

8. The method of claim 8 wherein the step of coupling the potential on said storage capacitor to said bit line comprises turning on a pair of transistors each having a gate connected to said word line, a first terminal coupled to said bit line, and a second terminal coupled to one side of said storage capacitor.