Test systems for obtaining a sample-on-the-fly event trace for an integrated circuit with an integrated debug trigger apparatus and an external pulse pin

• US 5,771,240 A
• Filed: 11/14/1996
• Issued: 06/23/1998
• Est. Priority Date: 11/14/1996
• Status: Expired due to Term

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett-Packard Company (HP Inc.)
• Inventors: Tobin, Paul G., Naaseh-Shahry, Hosein
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): Iqbal, Nadeem
• Application Number:
  US08/749,189
• Time in Patent Office: 586 Days
• Field of Search: 371/22.1, 371/22.32, 371/22.5, 371/22.6, 371/27.7, 371/22.31, 395/500, 395/181, 395/183.06, 395/183.07, 395/183.21, 395/183.01, 395/183.1, 395/183.11, 395/183.15, 364/550, 364/580, 364/489, 324/500, 324/512
• US Class Current: 714/724
• CPC Class Codes: G01R 31/31705 Debugging aspects, e.g. using test circuits for debugging, using dedicated debugging test circuits generation of test sequences therefor G01R31/31835, using scan test therefor G01R31/318544
• CPC Class Codes: G01R 31/318555 Control logic

Abstract

Presented is test system for use in debugging functional and electrical failures of an integrated circuit. The test system includes a diagnostics retrieval system and a test access port retrieval system external to the integrated circuit under test, and a debug trigger apparatus and test access port within the integrated circuit under test. The programmable debug trigger apparatus which resides internal and integral to the integrated circuit generates a trigger capture signal within a programmed delay after a set of monitored integrated circuit signals matches a programmed trigger condition. The test access port of the integrated circuit monitors a plurality of test nodes located throughout the integrated circuit and latches a set of test node signals present on test nodes located throughout the integrated circuit when it receives a trigger capture signal from the debug trigger apparatus. The trigger capture signal is also output to an external pin of the integrated circuit as an external pulse signal to indicate that the test access port has been latched and may be downloaded by the test access port retrieval system. The integrated circuit also includes a reset input for resetting the integrated circuit to an initial state. The diagnostics retrieval system is configured to program the programmable debug trigger apparatus in the integrated circuit to set up a trigger condition and to set the programmed delay to a first delay value. The diagnostics retrieval system then initiates operation of the integrated circuit and monitors the external pulse signal. When it receives an external pulse signal, the diagnostics retrieval system causes the test access port retrieval system to download a first set of test node signals from the test access port. The diagnostics retrieval system may then reset the integrated circuit, reprogram the trigger condition, and set the programmed delay to a second delay value which is a known increment greater than the first delay value, and the process is repeated to obtain a second set of downloaded test node signals. The process may be repeated to collect as many trigger event samples as are needed to form a useful trace of test node events for use in debugging functional and electrical failures of the integrated circuit under test.

Claims

1. A test system for debugging functional and electrical failures of an integrated circuit, comprising:

a programmable debug trigger apparatus disposed internal and integral to said integrated circuit for generating a trigger capture signal a programmed time delay after a plurality of integrated circuit signals satisfy a predetermined relationship to a programmed trigger event;

a test access port (TAP) disposed internal and integral to said integrated circuit comprising a TAP latch, said TAP latch coupled to a plurality of test nodes internal to said integrated circuit and responsive to said trigger capture signal for latching a plurality of test node signals present on said plurality of test nodes when said trigger capture signal is received;

an external output of said integrated circuit coupled to said TAP and responsive to said trigger capture signal for outputting an external output signal to indicate that said TAP latch has been latched;

a reset input of said integrated circuit for resetting said integrated circuit to an initial state;

a test access port retrieval system coupled to said TAP; and

a diagnostics retrieval system coupled to said integrated circuit and configured to reset said integrated circuit to said initial state, to program said programmed trigger event to a predetermined trigger capture event and said programmed time delay to a first delay value, to receive said external output signal, and to retrieve said plurality of test node signals from said TAP latch when said external output signal indicates that said TAP latch has been latched.

2. The test system of claim 1, said diagnostics retrieval system further configured to reset the integrated circuit again, to program said programmed trigger event to said predetermined trigger capture event and said programmed time delay to a second delay value which is incrementally greater than said first delay value, to receive said external output signal, and to retrieve said plurality of test node signals from said TAP latch when said external output signal indicates that said TAP latch has been latched.

3. The test system of claim 1, said diagnostics retrieval system comprising:

storage means for storing said plurality of test node signals retrieved by said test access port retrieval system.

4. The test system of claim 1, said diagnostics retrieval system comprising:

displaying means for displaying said plurality of test node signals retrieved by said test access port retrieval system.

5. The test system of claim 1, wherein said test access port retrieval system retrieves said plurality of test node signals from said test access port via a serial line using a JTAG protocol.

6. The test system of claim 1, wherein said debug trigger apparatus comprises:

a plurality of programmable trigger registers disposed internal and integral to said integrated circuit, each trigger register configured to receive a plurality of integrated circuit signals, to compare each of said plurality of integrated circuit signals of said integrated circuit to a programmed trigger condition, and to produce a trigger match signal when said plurality of integrated circuit signals match said programmed trigger condition;

a plurality of programmable trigger function blocks disposed internal and integral to said integrated circuit, each trigger function block coupled to receive a plurality of said trigger match signals and performing a programmed boolean minterm function on the monitored trigger match signals to produce a trigger capture signal; and

a programmable timer disposed internal and integral to said integrated circuit enabled by said trigger capture signal of a first corresponding one of said programmable trigger function blocks to generate a timer enable signal upon completion of a programmed time delay.

7. The debug trigger apparatus of claim 6, further comprising:

a programmable iteration counter disposed internal and integral to said integrated circuit and coupled to receive said trigger capture signal of a second corresponding one of said programmable trigger function blocks, said programmable iteration counter generating an iteration count enable signal upon receipt of said trigger capture signal of said second corresponding one of said programmable trigger function blocks a programmed iteration count number of times.

8. The debug trigger apparatus of claim 7, wherein one or more of the plurality of trigger function blocks is configured to further monitor said iteration counter enable signal and to include said iteration counter enable signal in performing said programmed boolean minterm function.

9. A method for collecting a continuous trace of internal test node signal events occurring on internal test nodes of an integrated circuit, comprising the steps of:

(a) setting a delay time to an initial value;

(b) resetting said integrated circuit to an initial state;

(c) programming a programmed trigger event of a programmable debug trigger apparatus to a predetermined trigger capture event and a programmed time delay to said delay time, said programmable debug trigger apparatus disposed internal and integral to said integrated circuit and configured to receive a plurality of integrated circuit signals of said integrated circuit and to generate a trigger capture signal said programmed time delay after said plurality of integrated circuit signals satisfy a predetermined relationship to said programmed trigger event;

(d) programming said internal programmable debug trigger apparatus to latch a test access port which monitors a plurality of test nodes internal to said integrated circuit upon the occurrence of said trigger capture signal and to signal an external pulse on an external pulse pin of said integrated circuit within a programmed delay after the occurrence of said trigger capture signal, wherein said programmed delay is set to said delay count;

(e) initiating operation of said integrated circuit;

(f) latching a plurality of test node signals present on a plurality of test nodes internal to said integrated circuit when said trigger capture signal is received;

(g) outputting an external output signal to indicate that said plurality of test node signals have been latched;

(h) retrieving said plurality of test node signals when said external output signal indicates that said plurality of test node signals have been latched;

(i) determining if more trace events are needed; and

(j) incrementing said delay count and repeating steps (b) through (i) if more trace events are needed.

10. The method of claim 9, further comprising the step of:

(k) storing said retrieved plurality of test node signals retrieved in step (h) in an event trace file.

11. The method of claim 9, further comprising the step of:

(l) displaying said retrieved plurality of test node signals retrieved in step (h) on an event trace screen.

12. A test system for debugging functional and electrical failures of an integrated circuit, comprising:

a programmable debug trigger apparatus disposed internal and integral to said integrated circuit for generating a trigger capture signal a programmed time delay after a plurality of integrated circuit signals satisfy a predetermined relationship to a programmed trigger event;

a test access port (TAP) disposed internal and integral to said integrated circuit comprising a TAP latch, said TAP latch coupled to a plurality of test nodes internal to said integrated circuit and responsive to said trigger capture signal for latching a plurality of test node signals present on said plurality of test nodes when said trigger capture signal is received;

an external output of said integrated circuit coupled to said TAP and responsive to said trigger capture signal for outputting an external output signal to indicate that said TAP latch has been latched;

a reset input of said integrated circuit for resetting said integrated circuit to an initial state;

a test access port retrieval system coupled to said TAP; and

a diagnostics retrieval system coupled to said integrated circuit and configured to reset said integrated circuit to said initial state, to program said programmed trigger event to a predetermined trigger capture event and said programmed time delay to a first delay value, to receive said external output signal, and to retrieve said plurality of test node signals from said TAP latch when said external output signal indicates that said TAP latch has been latched, to reset the integrated circuit again, to program said programmed trigger event to said predetermined trigger capture event and said programmed time delay to a second delay value which is incrementally greater than said first delay value, to receive said external output signal, and to retrieve said plurality of test node signals from said TAP latch when said external output signal indicates that said TAP latch has been latched;

wherein said programmable debug trigger apparatus comprises;

a plurality of programmable trigger registers disposed internal and integral to said integrated circuit, each trigger register configured to receive a plurality of integrated circuit signals, to compare each of said plurality of integrated circuit signals of said integrated circuit to a programmed trigger condition, and to produce a trigger match signal when said plurality of integrated circuit signals match said programmed trigger condition;

a plurality of programmable trigger function blocks disposed internal and integral to said integrated circuit, each trigger function block coupled to receive a plurality of said trigger match signals and performing a programmed boolean minterm function on the monitored trigger match signals to produce a trigger capture signal; and

a programmable timer disposed internal and integral to said integrated circuit enabled by said trigger capture signal of a first corresponding one of said programmable trigger function blocks to generate a timer enable signal upon completion of a programmed time delay.

13. The test system of claim 12, said debug trigger apparatus further comprising:

a programmable iteration counter disposed internal and integral to said integrated circuit and coupled to receive said trigger capture signal of a second corresponding one of said programmable trigger function blocks, said programmable iteration counter generating an iteration count enable signal upon receipt of said trigger capture signal of said second corresponding one of said programmable trigger function blocks a programmed iteration count number of times.

14. The test system of claim 13, wherein one or more of the plurality of trigger function blocks of the debug trigger apparatus is configured to further monitor said iteration counter enable signal and to include said iteration counter enable signal in performing said programmed boolean minterm function.