Processor having a bus interconnect which is dynamically reconfigurable in response to an instruction field
First Claim
1. A processor, comprising:
- an instruction sequencer configured to execute instructions having an opcode field and a bus configuration field, wherein said instruction sequencer is configured to produce at least one control signal in response to a first encoding of said bus configuration field; and
a bus interconnect coupled to receive said control signal from said instruction sequencer, said bus interconnect including a first plurality of buses and a second plurality of buses, wherein said bus interconnect is configured to route data from one of said first plurality of buses to one of said second plurality of buses if said control signal is asserted,wherein data from said one of said first plurality of buses is prevented from being routed to said one of said second plurality of buses if said control signal is deasserted.
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Accused Products
Abstract
A processor employing a dynamically configurable bus interconnect is provided. The interconnect routes data between functional units and memories included within the processor in response to an instruction field. As opposed to a particular hard-wired interconnect, the dynamically variable interconnect may be modified to form an optimum interconnect for the particular algorithm being executed. Still further, the interconnect may be modified between several configurations during the execution of the algorithm, as often as each clock cycle. Because an instruction field is used to directly specify the configuration of the interconnect during execution of that instruction, control over the interconnect is afforded to the programmer writing the code which implements a particular algorithm.
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Citations
18 Claims
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1. A processor, comprising:
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an instruction sequencer configured to execute instructions having an opcode field and a bus configuration field, wherein said instruction sequencer is configured to produce at least one control signal in response to a first encoding of said bus configuration field; and a bus interconnect coupled to receive said control signal from said instruction sequencer, said bus interconnect including a first plurality of buses and a second plurality of buses, wherein said bus interconnect is configured to route data from one of said first plurality of buses to one of said second plurality of buses if said control signal is asserted, wherein data from said one of said first plurality of buses is prevented from being routed to said one of said second plurality of buses if said control signal is deasserted. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A method for efficient data routing in a processor, comprising:
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encoding a connection between a first output of a first functional unit and a first input of a second functional unit within a first field of an instruction; detecting said first field upon execution of said instruction; asserting at least one control signal upon detection of said first field; routing data from said first output to said first input in a bus interconnect upon assertion of said at least one control signal, and preventing routing of data from said first output to said first input upon deassertion of said at least one control signal. - View Dependent Claims (16, 17, 18)
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Specification