Event driven programmer logic controller processor arrangement with buffered inputs and method of operation of the same

• US 5,771,374 A
• Filed: 08/14/1995
• Issued: 06/23/1998
• Est. Priority Date: 08/16/1994
• Status: Expired due to Term

• Current Assignee: Motorola Solutions, Inc.
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Burshtein, Anat, Scop, Shlomo, Geller, Haim
• Primary Examiner(s): Kim, Kenneth S.
• Application Number:
  US08/514,548
• Time in Patent Office: 1,044 Days
• Field of Search: 364/140, 364/579, 395/250, 395/736, 395/739, 395/557
• US Class Current: 713/502
• CPC Class Codes: G05B 19/054 Input/output
• CPC Class Codes: G05B 2219/1152 I-O module delivers interrupt on event, store port and 10ms timestamp in buffer
• CPC Class Codes: G05B 2219/1171 Detect only input variation, changing, transition state of variable
• CPC Class Codes: G05B 2219/15063 Real time clock

Abstract

A processor arrangement is described having a programmer logic controller (PLC) operating to a ladder diagram process. A number of event inputs (11-15) are provided connected to an interrupt buffer (31), in turn connected to a real time clock (32), for recording times of events of signals received on the event inputs and generating interrupts. Sequential storage locations in a cyclical buffer (60) store interrupts and their event times, where events occurring within a predetermined incremental time window are stored, with their event times, in a storage location for that time window. Each location of the cyclical buffer is inspected in sequence upon each new step of the sequential process. The PLC is arranged to operate on any events stored in the buffer which are affected by the new step of the sequential process before proceeding to the next step of the sequential process.

Claims

1. A processor arrangement comprising:

a programmer logic controller operating to a ladder diagram process comprising a sequence of instructional steps of a sequential process;

a number of event inputs connected to an interrupt buffer, in turn connected to a real time clock, for recording times of events of signals received on the event inputs and generating interrupts,

a cyclical buffer comprising sequential storage locations for storing interrupts and their event times;

event retrieval means for inspecting each location of the cyclical buffer sequentially upon each new instructional step of the sequential process;

wherein the programmer logic controller is arranged to operate on any event inputs stored in the cyclical buffer which are affected by the new step of the sequential process before proceeding to the next step of the sequential process.

2. A processor according to claim 1, wherein the cyclical buffer is formed in random access memory.

3. A method of operating a programmer logic controller operating to a ladder diagram process having a sequence of instructional steps of a sequential process, including instructions involving initiating of timers upon the occurrence of events;

comprising the steps of;

receiving event signals at event inputs on the occurrence of events;

recording times of the event signals received on the event inputs and generating interrupts on the occurrence of the events;

storing in a cyclical buffer comprising sequential storage locations, interrupts and their event times;

inspecting each location of the cyclical buffer sequentially upon each new instructional step of the sequential process, and

operating on any events stored in the buffer which are affected by the new step of the sequential process before proceeding to the next step of the sequential process.

4. A method according to claim 3, wherein a step of the sequential process is executable to a minimum predetermined time resolution and the times of the event signals are recorded to a resolution greater than the resolution of the steps of the sequential process.

5. A method according to claim 3, wherein the step of operating comprises inserting an indicator into the cyclical buffer in a new location determined by the step and the event, for running a logical equation at a time corresponding to the new location in the buffer.

6. A method according to claim 5, wherein the step of inserting comprises measuring a delay time predetermined by the step in the sequential process and selecting a location in the buffer offset from the storage location corresponding to the predetermined incremental time window by a number of buffer locations corresponding to the delay time.

7. A method according to claim 3, wherein event times are recorded to a predetermined resolution on a micro scale and wherein event inputs are monitored over a time period on a macro scale and when a time-out period is exceeded on the macro scale during which no events are read, the method defaults to a process of receiving events signals at event inputs on the occurrence of events, scanning the event inputs to record events, performing a ladder diagram process having a sequence of instructions and operating on the events recorded and scanned and repeating the process.