Membrane type integrated inductor and the process thereof

• US 5,773,870 A
• Filed: 09/10/1996
• Issued: 06/30/1998
• Est. Priority Date: 09/10/1996
• Status: Expired due to Term

• Current Assignee: National Science Council
• Original Assignee: National Science Council
• Inventors: Su, Shyang, Sheu, Jeng Tzong, Chuang, Kuen Joung
• Primary Examiner(s): Ngo , Ngan V.
• Application Number:
  US08/709,827
• Time in Patent Office: 658 Days
• Field of Search: 257/531, 336/65, 336/223, 336/232
• US Class Current: 257/531
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A membrane type integrated inductor includes an integrated inductor laid out on the upper plane of a membrane. The process to manufacture a membrane type integrated inductor includes the following steps: forming a thin dielectric layer at the outer portion of a substrate; forming a wire-wound integrated inductor thin dielectric layer with the known technique; defining an open window on the back of the substrate below the inductor through the backside etch; and forming a membrane type integrated inductor by using the thin dielectric layer on the silicon substrate as the etching stop. One embodiment uses silicon dioxide as the membrane layer. The low dielectric constant of SiO₂ may be used to lower the power loss during the lay out of the circuit parts, to effectively raise the induction value, to lower the parasitic capacitance, to increase the resonance frequency, to decrease the volume of the chip which the inductor utilized, and to raise the quality factor.

Claims

1. A membrane type integrated inductor comprising:

a substrate having a top surface,

a membrane dielectric layer fabricated on the entire top surface of the substrate, and

an integrated inductor formed on the membrane dielectric layer,;

wherein the substrate below the membrane where the integrated inductor is formed is etched away using the membrane dielectric layer as an etching stop.

2. A membrane type integrated as claimed in claim 1 wherein the membrane dielectric layer is silicon dioxide, silicon nitride, silicon carbide, diamond, quasi diamond, poly silicon, single silicon crystal, or gallium arsenide.

3. A membrane type integrated inductor as claimed in claim 1 wherein the thickness of the membrane dielectric layer is from 0.5 μ

m to 20 μ

m.

4. A membrane type integrated inductor as claimed in claim 1 wherein the membrane dielectric layer is a compound layer formed by a plurality of different dielectric layers.

5. A membrane type integrated inductor as claimed in claim 1 wherein the substrate is silicon, gallium arsenide or aluminiuml oxide.