Antifuse circuit using standard MOSFET devices

• US 5,774,011 A
• Filed: 05/28/1997
• Issued: 06/30/1998
• Est. Priority Date: 12/21/1995
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Tong, Ming Ho, Au, Wai-Ming William, Nowak, Edward Joseph
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): ZWEIZIG, JEFFERY SHAWN
• Application Number:
  US08/864,254
• Time in Patent Office: 398 Days
• Field of Search: 327/525
• US Class Current: 327/525
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A programmable device is formed from a field-effect transistor. Specifically, the present invention generally related to integrated circuit (IC) structures and more particularly, to an improved antifuse structure for use in programming redundant and customizable IC chips. The anti-fuse is NFET made of MOS material and formed at a face of a semiconductor layer having an n-type doped source, and drain region, and a p-type doped channel region separating the source and drain regions. The device is programmed by applying a high voltage to the NFET drain to form a hot spot located along the channel width of the drain and thereby forming a bridge, which now has less resistance than the surrounding channel material, to the NFET source.

Claims

1. An integrated circuit having an antifuse circuit for enabling a discretionary circuit, comprising:

a) a first node having a programmable high voltage applied thereto;

b) a PFET having;

a gate,

a source coupled to the first node, and

a drain coupled to a second node and the discretionary circuit;

c) a programmable circuit, coupled to the gate of the PFET, for pulling the PFET gate voltage high and low; and

d) an NFET having a drain electrode coupled to the second node, the NFET gate having a channel region with a predetermined width and length that is shorted upon application of the programmable high voltage.

2. The integrated circuit of claim 1 further comprising:

an integrated circuit input pad, coupled to the first node, for applying the programmable high voltage to the first node.

3. The integrated circuit of claim 1 wherein the NFET is shorted by the programmable high voltage creating a hot spot in the NFET channel region.

4. The integrated circuit of claim 1 wherein the source of the NFET is coupled to the gate.

5. The integrated circuit of claim 1 wherein the gate of the NFET is coupled through a diode to ground.

6. The integrated circuit of claim 1 wherein the gate of the NFET is coupled to a floating node.

7. The integrated circuit of claim 1 wherein the gate of the NFET is coupled to a second control circuit.

8. The integrated circuit of claim 1 wherein the gate of the NFET is coupled to ground.

9. The integrated circuit of claim 3 wherein the high voltage is between 6 to 9 volts.

10. The integrated circuit of claim 3 wherein the high voltage is about 6.5 volts.

11. The integrated circuit of claim 10 wherein the NFET channel width is about 10 μ

m and channel length is about 0.5 μ

m.