Encoding arrangement and method for encoding(N-1)-bit information words into N-bit channel words and decoding arrangement and method for decoding the channel words into information words

• US 5,774,077 A
• Filed: 02/02/1996
• Issued: 06/30/1998
• Est. Priority Date: 02/08/1995
• Status: Expired due to Fees

• Current Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Original Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Inventors: Schouhamer Immink, Kornelis A.
• Primary Examiner(s): Gaffin, Jeffrey A.
• Assistant Examiner(s): JEAN PIERRE, PEGUY
• Application Number:
  US08/595,534
• Time in Patent Office: 879 Days
• Field of Search: 341/50, 341/59, 341/58, 341/106, 341/67, 341/69
• US Class Current: 341/50
• CPC Class Codes: H03M 5/145 Conversion to or from block codes or representations thereof

Abstract

Encoding arrangement and method for encoding (n-1) information words into n-bit channel words and decoding arrangement and method for decoding the channel words into information words. The encoding arrangement is to obtain a channel signal of concatenated channel words comprising a bit sequence having at most k `zeroes` between `ones`. The encoding arrangement comprises input means for receiving the (n-1)-bit information words, converting means for converting the (n-1) bit information words into n-bit channel words and output means for supplying the channel signal. A corresponding decoding arrangement is also disclosed.

Claims

1. Encoding arrangement for encoding (n-1)-bit information words into n-bit channel words so as to obtain a channel signal of concatenated channel words, the channel signal being a bit sequence having the virtue that at most k `zeros` between `ones` occur, the encoding arrangement comprising:

input means for receiving the (n-1)-bit information words;

converting means for converting the (n-1)-bit information words into n-bit channel words; and

output means for supplying the channel signal of concatenated n-bit channel words, wherein the converting means comprises;

inserting means for inserting one bit of a first or a second binary value in between a specified first and a second neighbouring bit position in each (n-1)-bit information word to form an n-bit channel word, a `zero` bit being inserted in between said specified first and second neighbouring position of any particular (n-1)-bit information word if the number of leading `zeros` at the leading end of said any particular information word exceeds a specified first integer number, or the number of trailing `zeros` at the trailing end of said any particular information word exceeds a specified second integer number; and

setting means for setting a logical value in a specified third bit position into a `one` value if the number of leading `zeros` exceeds said specified first number, and for setting a logical value in a specified fourth bit position into a `one` value if the number of trailing `zeros` exceeds said specified second number, the specified third bit position being one of a specified third number of leading bit positions of said any particular information word, the specified fourth bit position being one of a specified fourth number of trailing bit positions of said any particular information word, the specified third number being equal to the specified first number plus one, the specified fourth number being equal to the specified second number plus one, n and k being integer values and the specified first and second numbers having a relationship with k,

the inserting means inserting a `zero` bit in between said specified first and second neighbouring position if a group of more than k consecutive bit positions in the any particular information word comprise all `zeros`, said group of more than k consecutive bit positions not comprising both the specified first and second bit positions.

2. Encoding arrangement as claimed in claim 1, wherein the inserting means is further adapted to insert a `one` bit in between said specified first and second neighbouring bit positions, otherwise.

3. Encoding arrangement as claimed in claim 1, wherein said group of more than k consecutive bit positions comprising all `zeroes` occurs at the leading side of the first and second bit positions in the any particular information word, said third bit position further coinciding with one of said group of more than k consecutive bit positions comprising all `zeroes`.

4. Encoding arrangement as claimed in claim 1, wherein said group of more than k consecutive bit positions comprising all `zeroes` occurs at the trailing side of the first and second bit positions in the any particular information word, said fourth bit position further coinciding with one of said group of more than k consecutive bit positions comprising all `zeroes`.

5. Encoding arrangement as claimed in claim 1, wherein said setting means is further adapted to set a logical value in a specified fifth bit position in said any particular information word into a `one` value if the number of leading `zeroes` exceeds said specified first number.

6. Encoding arrangement as claimed in claim 5, wherein said fifth bit position is not coinciding with any of the positions of the specified third number of leading bit positions or the specified fourth number of trailing bit positions of the any particular information word.

7. Encoding arrangement as claimed in claim 5, wherein said setting means is further adapted to set a logical value in a specified sixth bit position in said any particular information word into a `one` value if the number of trailing `zeroes` exceeds said specified second number.

8. Encoding arrangement as claimed in claim 7, wherein said sixth bit position is not coinciding with any of the positions of the specified third number of leading positions or the specified fourth number of trailing positions of the any particular information word.

9. Encoding arrangement as claimed in claim 7, wherein said sixth bit position is said second bit position.

10. Encoding arrangement as claimed in claim 7, wherein said setting means is further adapted to set the logical value in said specified fifth bit position in said any particular information word into a `one` value if a group of more than k consecutive bit positions in the any particular information word comprising all `zeroes` occurs at the leading side of the first and the second bit position in the any particular information word, the said group not comprising both the first and the second bit positions.

11. Encoding arrangement as claimed in claim 10, wherein said setting means is further adapted to set the logical value in said specified sixth bit position in said any particular information word into a `one` value if a group of more than k consecutive bit positions in the any particular information word comprising all `zeroes` occurs at the trailing side of the first and the second bit position in the any particular information word, the said group not comprising both the first and the second bit positions.

12. Encoding arrangement as claimed in claim 11, wherein said setting means is adapted to set the logical value in said specified sixth bit position to `zero`, otherwise.

13. Encoding arrangement as claimed in claim 12, wherein if the logical value in said fifth bit position is set to `one` by the setting means and the logical value in said sixth bit position is set to `zero` by the setting means, the setting means is further adapted to reposition logical values originally present in said fifth and sixth bit positions to seventh and eighth bit positions in said any particular information word, said seventh and eighth bit positions lying within said specified third number of leading bit positions and lying within said group of more than k consecutive bit positions occurring at the leading side of the first and second bit positions, said seventh and eighth bit positions not coinciding with said third bit position.

14. Encoding arrangement as claimed in claim 12, wherein if the logical value in said fifth bit position is set to `zero` and the logical value in said sixth bit position is set to `one` by the setting means, the setting means is further adapted to reposition the logical values originally present in said fifth and sixth bit positions to ninth and tenth bit positions in said information word, said ninth and tenth bit positions lying within said specified fourth number of trailing bit positions and lying within said group of more than k consecutive bit positions occurring at the trailing side of said first and second bit positions, said ninth and tenth bit positions not coinciding with said fourth bit position.

15. Encoding arrangement as claimed in claim 10, wherein said setting means is adapted to set the logical value in said specified fifth bit position to `zero`, otherwise.

16. Encoding arrangement as claimed in claim 7, wherein if the logical value in said fifth bit position is set to `one` by the setting means and the logical value in said sixth bit position is set to `zero` by the setting means, the setting means is further adapted to reposition logical values originally present in said fifth and sixth bit positions to seventh and eighth bit positions in said any particular information word, said seventh and eighth bit positions lying within said specified third number of leading bit positions, said seventh and eighth bit positions not coinciding with said third bit position.

17. Encoding arrangement as claimed in claim 16, wherein if the logical value in said fifth bit position is set to `zero` and the logical value in said sixth bit position is set to `one` by the setting means, the setting means is further adapted to reposition the logical values originally present in said fifth and sixth bit positions to ninth and tenth bit positions in said any particular information word, said ninth and tenth bit positions lying within said specified fourth number of trailing bit positions, said ninth and tenth bit positions not coinciding with said fourth bit position.

18. Encoding arrangement as claimed in claim 5, wherein said fifth bit position is said first bit position.

19. Encoding arrangement as claimed in claim 1, wherein (n-1) is an even integer number and said first and second bit positions are the central bit positions in the any particular information word.

20. Encoding arrangement as claimed in claim 19, wherein the specified first number equals the specified second number and k=(n-1)/2.

21. Encoding arrangement as claimed in claim 1, wherein said third bit position is the leading bit position of the any particular information word, and said fourth bit position is the final bit position of the any particular information word.

22. Encoding arrangement as claimed in claim 1, wherein the specified first number equals the specified second number.

23. Encoding arrangement as claimed in claim 22, wherein (n-1) is an integer multiple of 4, and the specified first number equals (n-1)/4.

24. Encoding arrangement as claimed in claim 1, wherein k>

{(n-1) div 2}/2.

25. Encoding arrangement as claimed in claim 1, wherein k>

2 1 +entier(n/3), where entier(n/3) equals the smallest integer larger than or equal to n/3.

26. Encoding arrangement as claimed in claim 1, wherein k equals the sum of the first and the second specified numbers.

27. Encoding arrangement as claimed in claim 1, further comprising shuffling means for carrying out a shuffling step said any particular information on an information word prior to encoding.

28. Encoding arrangement as claimed in claim 27, wherein the shuffling step is such that bits stored in at least two neighbouring bit positions in the any particular information word are moved to at least two bit positions that may be affected by the setting means so as to obtain a shuffled information word.

29. Encoding arrangement as claimed in claim 1, further comprising digital sum value determining means for generating a control signal in response to a digital sum value of said channel signal, the setting means being further adapted to set a logical value in at least one further specified bit position into a `one` value in response to said control signal, the at least one further specified bit position being one of the specified third number of leading bit positions of the any particular information word or one of the specified fourth number of trailing bit positions of the any particular information word, said at least one further specified bit position not coinciding with one of other specified bit positions.

30. Encoding method for encoding a sequence of (n-1)-bit information words into a sequence of n-bit channel words, the encoding method being carried out in the encoding arrangement as claimed in claim 1.

42. Decoding arrangement as claimed in claim 20, further comprising deshuffling means for carrying out a deshuffling step on the information words after decoding.

43. Decoding arrangement as claimed in claim 42, wherein the deshuffling step is such that bits stored in at least two bit positions in an information word that may have been affected by the setting means are repositioned in at least two neighbouring bit positions so as to obtain a deshuffled information word.

44. Decoding arrangement as claimed in claim 21, wherein the setting means is further adapted to set logical value in at least one further specified bit position into a `one` value in the absence of the first control signal, the at least one further specified bit position being one of the specified third number of leading bit positions of the information words or one of the specified fourth number of trailing bit positions of the information words, said at least one further specified bit position not coinciding with one of the other specified bit positions.

31. Decoding arrangement for decoding a channel signal of concatenated n-bit channel words into an information signal of concatenated (n-1)-bit information words, the channel signal being a bit sequence having the virtue that at most k `zeros` between `ones` occur, the decoding arrangement comprising:

input means for receiving the n-bit channel words;

reconverting means for reconverting the n-bit channel words into (n-1)-bit information words;

output means for supplying the (n-1)-bit information words, wherein the reconverting means comprises;

detection means for detecting a binary value in a specified first bit position in the n-bit channel words, and for supplying a first control signal upon detecting a logical `one` value;

deleting means for deleting a specified second bit position in the n-bit channel words so as to obtain (n-1)-bit converted channel words, wherein the first specified bit position is the second specified bit position,

the output means being adapted to supply the (n-1)-bit converted channel words as the (n-1)-bit information words upon occurrence of the first control signal for said converted channel words, and

setting means for setting a logical value in a specified third bit position lying within a specified first number of leading bit positions in said converted channel word into a `zero` value, or for setting a logical value in a specified fourth bit position lying within a specified second number of trailing bit positions in said converted channel word into a `zero` value, or both, in the absence of the first control signal, so as to obtain an (n-1)-bit information word, the setting means supplying the (n-1)-bit information words to the output means in the absence of the first control signal, n and k being integer values.

32. Decoding arrangement as claimed in claim 31, wherein the detection means is further adapted to detect the binary values in specified fifth and sixth bit positions in the n-bit channel words, for supplying a second control signal upon detection of a logical `one` value in said specified fifth bit position and a logical `zero` value in said sixth bit position, the setting means being further adapted to reposition logical values present in seventh and eighth bit positions lying within said specified first number of leading bit positions to said fifth and sixth bit positions respectively and to set logical values in said seventh and eighth bit position to `zero`, said seventh and eighth bit positions not coinciding with said third bit position.

33. Decoding arrangement as claimed in claim 32, wherein the detection means is further adapted to supply a third control signal upon detection of a logical `zero` value in said specified fifth bit position and a `one` value in said specific sixth bit position, the setting means being further adapted to reposition logical values present in ninth and tenth bit positions lying within said specified second number of trailing bit positions to said fifth and sixth bit positions respectively and to set logical values in said ninth and tenth bit position to `zero`, said ninth and tenth bit positions not coinciding with said fourth bit position.

34. Decoding arrangement as claimed in claim 31, wherein n is an odd integer number and said first position is the central bit position in the channel word.

36. Decoding arrangement as claimed in claim 33, wherein (n-1) is an integer multiple of 4, and the specified first number equals (n-1)/4.

37. Decoding arrangement as claimed in claim 31, wherein said third bit position is the leading bit position of the channel word, and said fourth bit position is the final bit position of the channel word.

38. Decoding arrangement as claimed in claim 31, wherein the specified first number equals the specified second number.

39. Decoding arrangement as claimed in claim 31, wherein k>

{(n-1) div 2}/2.

40. Decoding arrangement as claimed in claim 31, wherein k >

1 +entier(n/3), where entier(n/3) equals the smallest integer larger than or equal to n/3.

41. Decoding arrangement as claimed in claim 31, wherein k equals the sum of the first and the second specified numbers.

45. Decoding method for decoding a sequence of n-bit channel words into a sequence of (n-1)-bit information words, the decoding method being carried out in the decoding arrangement as claimed in claim 31.

35. Decoding arrangement as claimed in claim 35, wherein the specified first number equals the specified second number and k=(n-1)/2.