Process for controlling an MPEG decoder

• US 5,774,206 A
• Filed: 12/19/1996
• Issued: 06/30/1998
• Est. Priority Date: 05/10/1995
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Cagent Technologies Incorporated
• Inventors: Baldwin, James Armand, Wasserman, Steve C., Mitsuoka, George
• Primary Examiner(s): Voeltz, Emanuel T.
• Assistant Examiner(s): ASSOUAD, PATRICK J
• Application Number:
  US08/769,575
• Time in Patent Office: 558 Days
• Field of Search: 364/514 R, 348/403, 348/416, 348/420, 348/426, 382/166, 382/232, 382/236, 382/246, 382/250, 395/200.77
• US Class Current: 709/247
• CPC Class Codes: H04N 19/42 characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/433 characterised by techniques for memory access
• CPC Class Codes: H04N 19/61 in combination with predictive coding
• CPC Class Codes: H04N 19/90 using coding techniques not provided for in groups H04N19/10-H04N19/85, e.g. fractals

Abstract

A process for decoding MPEG encoded image data stored in a system memory utilizing a configurable image decoding apparatus. The process comprises the steps of: (a) extracting macroblock information from said MPEG encoded image data, the macroblocks containing image data and motion compensation data; (b) extracting a series of parameters from the MPEG encoded image data for decoding the MPEG encoded data; (c) determining quantization factors from the encoded image data; (d) configuring the configurable image decoding apparatus, including (i) configuring a means for parsing the macroblock data into motion vectors and image data with the series of parameters with the parameters for decoding the encoded data; (ii) configuring a means for performing inverse quantization with the quantization co-efficients; (e) determining a decoding order of the extracted macroblock information to be decoded; (f) providing said extracted macroblock information to the parsing means in the decoding order; (g) combining decoded image data with motion vectors extracted by the parsing means; and (h) storing the combined data in the system memory.

Claims

1. A process for decoding MPEG encoded image data stored in a system memory utilizing a configurable image decoding apparatus, said process comprising the steps of:

(a) establishing in the system memory a series of buffers, including a display buffer, a reference buffer and a strip buffer;

(b) extracting macroblock information from said MPEG encoded image data, the macroblocks containing image data and motion compensation data;

(c) extracting a series of parameters from the MPEG encoded image data for decoding the MPEG encoded data;

(d) determining quantization factors from the encoded image data;

(e) configuring the configurable image decoding apparatus, including

(i) configuring a means for parsing the macroblock data into motion vectors and image data with the series of parameters for decoding the encoded data;

(ii) configuring a means for performing inverse quantization with the quantization coefficients;

(f) determining a decoding order of the extracted macroblock information to be decoded;

(g) providing said extracted macroblock information to the parsing means in the decoding order;

(h) combining decoded image data with motion vectors extracted by the parsing means; and

(i) storing the combined data in the system memory.

2. The process for decoding according to claim 1 wherein said step (i) comprises storing decoded image data in the strip buffer and the reference buffer.

3. The process for decoding according to claim 1 wherein said step (e) (i) further comprises obtaining, from the series of parameters, image size data, forward and backward r values, and forward and backward prediction values, and writing said values to a configuration register in the means for parsing.

4. A configurable de coding system in a host system, the host system including host system memory, a host system memory controller and a central processing unit, the system memory storing MPEG encoded video data including a video sequence comprising one or more groups of pictures, each picture comprised of a plurality of slices of macroblocks, each macroblock comprising at least four blocks, said blocks comprising coded picture data and coded motion compensation data, the system comprising:

instruction means for configuring the system memory to include a reference buffer, a display buffer, and a strip buffer;

instruction means for extracting, from said MPEG encoded data, the video sequence and for extracting context information from the video sequence, the context information for decoding the video sequence comprising header information, picture type, frame size, image size and quantization tables, and for extracting said slices of macroblocks from a picture in each group of pictures;

a configurable MPEG decoder, the MPEG decoder including configurable parsing means for extracting picture and motion vector data, means for performing entropy decoding on the picture data, programmable means for performing inverse quantization on the decoded picture data, means for performing inverse zig-zagging, and means for taking the inverse discrete cosine transform of the picture data co-efficients;

configuration control means, operatively coupled to the means for extracting and the configurable MPEG decoder, for configuring the MPEG decoder by programming the parsing means with said picture type, frame size and image size, for configuring the means for performing inverse quantization with said quantization tables;

configurable motion compensation means, coupled to the configurable MPEG decoding unit and the system memory;

configurable video output DMA controlling means, coupled to the motion compensation means and the system memory; and

configurable video output formatting means.

5. The decoding system of claim 4 wherein the instruction means for configuring further includes means for configuring the system memory to include a data buffer, wherein data to be decoded is provided in said data buffer and identified by a plurality of addresses.

6. The decoding system of claim 5 wherein the instruction means for configuring further includes means for configuring the configurable MPEG decoder with said context information.

7. The decoding system of claim 6 wherein said configurable parsing means includes a configuration register, said register being configured to contain said context information, the context information including image size data on the material being decoded.

8. The decoding system of claim 6 wherein said context information includes at least the picture coding type, the forward r size, and the backward r size of the data to be decoded.

9. The decoding system of claim 8 wherein said programmable means for performing inverse quantization includes a quantization table register.

10. The decoding system of claim 5 wherein the reference buffers are operatively coupled to the motion compensation unit.

11. The decoding system of claim 5 wherein the buffers include a strip buffer, operatively coupled to the motion compensation unit and the video output DMA controller, storing decoded image data.

12. A process for decoding encoded video images in a host system, the host system including a system memory and a central processing unit, the system memory containing image data to be decoded, comprising:

providing a configurable parsing means, an configurable inverse quantization means, an inverse zig-zag unit, and an inverse discrete cosine transform unit;

defining, in said system memory, a first and second display buffers, a strip buffer, a first and second reference buffers, and a bitstream buffer;

extracting from the image data, a video sequence and a series of sequence parameters contained in the video sequence, said sequence parameters including information for decoding at least one picture in the stream;

outputting the sequence parameters to the configurable parsing means;

outputting the image data to the configurable parsing means;

writing decoded data to the strip buffer and to a video output formatter and to the first and second reference buffers; and

outputting from the display means to the first and second reference buffers.

13. An apparatus for processing encoded image data wherein image data is used to produce an image composed of a matrix of pixels, the apparatus being included in a host system, the host system including a system memory and a processor, the apparatus comprising:

a first input port for receiving a first encoded image-defining signal, where said first encoded image defining signal is divisible into at least one pixel defining component, where each pixel defining component may comprise motion vector data or pixel value data;

a first input/output port for receiving and outputting a handshaking signal;

a second input/output port for outputting motion vector data and receiving reference data defining a reference frame relative to the motion vector data;

an output port for outputting decoded image data;

control means, operatively instructing the central processing unit to provide encoded image information into the first input port, operatively instructing decoded data from the output port to be written to system memory, instructing reference information to be input to the second input/output port and instructing decoded data and reference information to be directed to a video output formatter, wherein the decoded data is written to a strip buffer and a reference buffer in the system memory from the output port.

14. A process for decoding coded image data in a host computer, the host computer including a host system memory, a central processing unit, decoding hardware, and video formatting hardware, the process including:

directing the CPU to parse the system memory into a series of buffers, including a display buffer, a reference buffer and a strip buffer, the instruction means;

reading the coded image data and ascertaining context information regarding information in the data to be decoded;

parsing the coded data into the slice level information and providing the information to the decoding hardware;

retrieving decoded picture data from the decoding hardware;

storing said decoded picture data in said reference buffers and in said strip buffer;

directing the reference buffer data to the decoding hardware;

outputting reference buffer information and decoded picture data to the video formatting hardware;

storing formatted decoded picture data in a display buffer in said system memory.

15. A process for decoding coded image data in a host computer, the host computer including a central processing unit (CPU) and system memory, the computer including a decoding processor, comprising the steps of:

(a) directing the CPU to perform the steps of

parsing the system memory into a series of buffers, including a display buffer, a reference buffer and a strip buffer;

reading the coded image data and ascertaining context information regarding information in the data to be decoded;

parsing the coded data into the slice level information and providing the information to the decoding processor;

(b) directing the decoding processor to perform the steps of

distributing coded motion vector information blocks and image data information blocks;

decoding the image data blocks into quantized coefficient blocks;

performing an inverse quantization on said quantized coefficient blocks to form pixel value blocks;

converting the pixel value blocks to pixel coefficients;

calculating the inverse discrete cosine transform of the pixel coefficients to produce pixel display values;

decoding the motion vector blocks into pixel motion vectors; and

adding the pixel motion vectors and pixel display values; and

(c) directing the CPU to perform the steps of;

retrieving decoded picture data from the decoding hardware;

storing said decoded picture data in said system memory;

directing the reference buffer data to the decoding hardware; and

storing formatted decoded picture data in a display buffer in said system memory.

16. A process for decoding coded image data in a host computer, the host computer including a host system memory, a central processing unit, decoding hardware, and video formatting hardware, the coded data including an nth stream of video data, an n+1 stream of video data and an n+m stream of video data, where n and m are integers, the process including:

directing the CPU to parse the system memory into a series of buffers, including a display buffer, a reference buffer and a strip buffer, the instruction means;

reading the coded image data and, for each said stream, ascertaining context information regarding the coded image data to be decoded;

parsing, for each stream, the coded data into the slice level information;

ordering the coded data and the context information into a stream decoding order;

providing the coded data and context information to the decoding hardware;

retrieving decoded picture data from the decoding hardware;

storing said decoded picture data in said reference buffers and in said strip buffer;

directing the reference buffer data to the decoding hardware;

outputting reference buffer information and decoded picture data to the video formatting hardware;

storing formatted decoded picture data in a display buffer in said system memory.

17. A process for decoding coded image data in a host computer, the host computer including a central processing unit (CPU) and system memory, the coded data including an nth stream of video data, an n+1 stream of video data and an n+m stream of video data, where n and m are integers the computer including a decoding processor, comprising the steps of:

(a) directing the CPU to perform the steps of

parsing the system memory into a series of buffers, including a display buffer, a reference buffer and a strip buffer;

reading the coded image data;

determining, for each said stream, context information regarding information in the data to be decoded;

parsing, for each stream, the coded data into the slice level information and providing the information to the decoding processor;

(b) directing the decoding processor to perform the steps of

distributing coded motion vector information blocks and image data information blocks;

decoding the image data blocks into quantized coefficient blocks;

performing an inverse quantization on said quantized coefficient blocks to form pixel value blocks;

converting the pixel value blocks to pixel coefficients;

calculating the inverse discrete cosine transform of the pixel coefficients to produce pixel display values;

decoding the motion vector blocks into pixel motion vectors; and

adding the pixel motion vectors and pixel display values; and

(c) directing the CPU to perform the steps of;

retrieving decoded picture data from the decoding hardware;

storing said decoded picture data in said system memory;

directing the reference buffer data to the decoding hardware; and

storing formatted decoded picture data in a display buffer in said system memory.