Planar redistribution structure and printed wiring device

• US 5,774,340 A
• Filed: 08/28/1996
• Issued: 06/30/1998
• Est. Priority Date: 08/28/1996
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Chang, Chi Shih, Egitto, Frank Daniel
• Primary Examiner(s): Picard, Leo P.
• Assistant Examiner(s): Vigushin, John B.
• Application Number:
  US08/697,655
• Time in Patent Office: 671 Days
• Field of Search: 361/767, 361/768, 361/771, 361/777, 361/780, 361/792, 361/794, 361/783, 257/691, 257/695, 257/700, 257/723, 257/778, 257/786, 174/255, 174/261, 174/262, 174/266, 333/247
• US Class Current: 361/771
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/5383 Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/5384 Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H05K 1/113 Via provided in pad; Pad over filled via
• CPC Class Codes: H05K 2201/0394 Conductor crossing over a hole in the substrate or a gap between two separate substrate parts
• CPC Class Codes: H05K 2201/09509 Blind vias, i.e. vias having one side closed
• CPC Class Codes: H05K 2201/09527 Inverse blind vias, i.e. bottoms outwards in multilayer PCB; Blind vias in centre of PCB having opposed bottoms
• CPC Class Codes: H05K 2201/09536 Buried plated through-holes, i.e. plated through-holes formed in a core before lamination
• CPC Class Codes: H05K 2201/096 Vertically aligned vias, holes or stacked vias
• CPC Class Codes: H05K 3/4602 characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
• CPC Class Codes: H05K 3/462 characterized by laminating only or mainly similar double-sided circuit boards
• CPC Class Codes: H05K 3/4623 the circuit boards having internal via connections between two or more circuit layers before lamination, e.g. double-sided circuit boards H05K3/462 takes precedence
• CPC Class Codes: Y10T 29/49126 Assembling bases
• CPC Class Codes: Y10T 29/49144 by metal fusion
• CPC Class Codes: Y10T 29/49165 by forming conductive walled aperture in base

Abstract

A self-supporting redistribution structure for directly mounting a semi-conductor chip to a multilayer electronic substrate is separately fabricated and then laminated to the multilayer substrate. The redistribution structure comprises a dielectric layer having plated vias communicating between its two major surfaces, redistribution lines and input/output pads on its upper major surface and joining patterns on its lower margin surface for electrical connection with the multilayer substrate. The metal plating in the plated vias of the redistribution device connects respective input/output pads on the upper surface of the redistribution structures with the joining patterns on its lower major surface. Input/output pads define an even (planar) topography with the redistribution lines to facilitate flip chip joining.

Claims

1. A planar redistribution structure for subsequent lamination to a printed wiring device, said structure having vias not exposed to a top surface of said structure, said structure comprising:

a fluoropolymer-based dielectric sheet having a top surface and a bottom surface;

said top surface comprising signal redistribution lines and input/output pads, said lines and pads being substantially the same height;

said bottom surface comprising a ground plane and joining patterns for signal, power and ground connections.

2. The structure of claim 1, wherein said ground plane comprises copper-invar-copper.

3. The structure of claim 1, where said signal redistribution lines fan out from an integrated circuit area array at small pitch to said input/output pads at large pitch.

4. The structure of claim 3, wherein blind vias formed by laser ablation interconnect said input/output pads to said joining patterns, and further wherein said top surface is free of via hole topology.

5. A planar redistribution structure for carrying at least one semiconductor chip and for subsequent lamination to a multilayer electronic substrate, said structure comprising

a dielectric layer having an upper major surface and a lower major surface, said dielectric layer defining a plurality of vias communicating between said upper and lower major surfaces wherein said vias are plated-through-holes,

a plurality of signal redistribution lines on said upper major surface for electrical connection to at least one semiconductor chip,

a plurality of input/output pads in electrical contact with selected ones of said signal redistribution lines, said input/output pads being carried on said upper major surface and communicating with respective vias in said dielectric layer, said input/output pads and said signal redistribution lines being substantially the same height whereby the upper surfaces of said signal redistribution lines and said input/output pads are essentially coplanar and wherein said plated-through-holes are formed from a metal plated on the interior surfaces of said vias, the metal in each plated-through-hole being in electrical contact with said respective input/output pads such that the tops of said plated-through-holes are defined by said input/output pads whereby the tops of said plated-through-holes define an even topography with said redistribution lines at the upper surface of said dielectric, and

a plurality of joining patterns on the lower major surface of said dielectric layer, said joining patterns communicating with respective vias in said dielectric layer wherein said joining patterns are larger in lateral dimension than said input/output pads.

6. The structure of claim 5, wherein said structure further includes a ground plane attached to the lower major surface of said dielectric layer, said ground plane being in electrical communication with at least one of said joining patterns.

7. The structure of claim 6, wherein at least one of said joining patterns is a power joining pattern for electrical connection to a source of electrical power, and further wherein at least one of said joining patterns is a signal joining pattern for electrical connection to a source of electrical signals, said power joining pattern and said signal joining pattern being electrically insulated from said ground plane.

8. The structure of claim 7, wherein said semi-conductor chip defines contact bumps for electrical connection with the signal redistribution lines of said redistribution structure, with said lines being arranged in a fan-out pattern, the center-to-center pitch of said vias being at least twice as great as the pitch between said contact bumps and said dielectric layer being no more than 100 μ

m thick.

9. The structure of claim 8, wherein said dielectric layer is about 50 μ

m thick and further wherein the pitch between said chip contact bumps is about 250 μ

m.

10. The structure of claim 9, wherein said dielectric layer is no more than 100 μ

m thick.

11. The structure of claim 10, wherein said dielectric layer is about 50 μ

m thick and further wherein the pitch between said chip contact bumps is about 250 μ

m.