Low-complexity direct conversion receiver for delay-and-correlate transmitted reference signaling

• US 5,774,492 A
• Filed: 08/02/1996
• Issued: 06/30/1998
• Est. Priority Date: 08/02/1996
• Status: Expired due to Term

• Current Assignee: General Electric Company
• Original Assignee: General Electric Company
• Inventors: Orlowsik, Eugene Joseph Jr., Ross, John Anderson Fergus
• Primary Examiner(s): TSE, YOUNG TOI
• Application Number:
  US08/691,253
• Time in Patent Office: 697 Days
• Field of Search: 375/200, 375/202, 375/206-210, 375/343, 375/367, 370/342, 370/47.9
• US Class Current: 375/142
• CPC Class Codes: H04B 1/70718 with asynchronous demodulation, i.e. not requiring code synchronisation

Abstract

A direct conversion receiver for a delay-and-correlate transmitted reference spread spectrum signaling method and apparatus is based on minimal component digital circuitry instead of analog delay and multiplier circuits. The method allows direct RF to baseband conversion and eliminates the need for an IF stage. The receiver includes an RF converter for converting a received direct sequence spread spectrum signal to baseband. An analog-to-digital converter samples the baseband signal at a rate greater than the chipping rate of the direct sequence spread spectrum signal. A delay stage coupled to the output of the analog-to-digital converter generates a delayed signal. Multiplier logic receives output signals from the analog-to-digital converter and the delay stage and, in response, generates control output signals. A counter responsive to the control output signals increments or decrements a count or recycles, depending on the decoded control output signals.

Claims

1. A direct conversion receiver for delay-and-correlate transmitted reference spread spectrum signaling, comprising:

means for converting a received direct sequence spread spectrum signal having a predetermined chipping rate to a baseband signal;

an analog-to-digital converter for sampling the baseband signal at a rate greater than the chipping rate of the direct sequence spread spectrum signal;

delay means coupled to the analog-to-digital converter output for generating a delayed signal;

multiplier logic for receiving output signals from said analog-to-digital converter and said delay means and for generating control output signals; and

a counter responsive to said control output signals for incrementing or decrementing a count or recycling.

2. The direct conversion receiver for delay-and-correlate transmitted reference spread spectrum signaling recited in claim 1 wherein said analog-to-digital converter samples only three different transmitted levels.

3. The direct conversion receiver for delay-and-correlate transmitted reference spread spectrum signaling recited in claim 2 wherein said analog-to-digital converter comprises a high comparator and a low comparator, respectively, for comparing the baseband signal to high and low thresholds.

4. The direct conversion receiver for delay-and-correlate transmitted reference spread spectrum signaling recited in claim 3 wherein said delay means comprises identical parallel first and second delay stages, said first delay stage being coupled to receive an output signal from said high comparator and the second delay stage being coupled to receive an output signal from said low comparator, and wherein input signals to said multiplier logic comprise an output signal C₁ of said high comparator, an output signal C₂ of said low comparator, an output signal C₁ (d) of said first delay stage, and an output signal C₂ (d) of said second delay stage.

5. The direct conversion receiver for delay-and-correlate transmitted reference spread spectrum signaling recited in claim 4 wherein the control signals produced by said multiplier logic are represented by first and second control signals X₀ and X₁, respectively, and said counter performs in response to the control signals as follows:

space="preserve" listing-type="tabular">______________________________________ X.sub.0 X .sub.1 ______________________________________ Increment 1 1 Decrement 1 0 Recycle 0 X ______________________________________

where the output state is Recycle whenever X₀ =0, and X represents any state.

6. The direct conversion receiver for delay-and-correlate transmitted reference spread spectrum signaling recited in claim 5 wherein the multiplier logic includes X₀ generation logic defined by the truth table:

space="preserve" listing-type="tabular">______________________________________ X.sub.0 C.sub.1 (d) C.sub.2 (d) C.sub.1 (d) C.sub.2 (d) C.sub.1 (d) C.sub.2 (d) C.sub.1 (d) C.sub.2 (d) C.sub.1 C.sub.2 0 0 0 1 1 0 1 1 ______________________________________ 0 0 1 X X 0 0 1 X X X X 1 0 X X X X 1 1 0 X X 1 ______________________________________

7. The direct conversion receiver for delay-and-correlate transmitted reference spread spectrum signaling recited in claim 6 wherein said X₀ generation logic comprises:

a first AND gate for receiving as input signals C₁, C₂, C₁ (d), and C₂ (d) for generating a logical output signal C₁ ·

C₂ ·

C₁ (d)·

C₂ (d);

a NOR gate for receiving as input signals C₁, C₂, C₁ (d), and C₂ (d) for generating a logical output signal C₁ ·

C₂ ·

C₁ (d)·

C₂ (d); and

a second AND gate for receiving the output signals of the first AND gate and the NOR gate to generate the first control signal X₀.

8. The direct conversion receiver for delay-and-correlate transmitted reference spread spectrum signaling recited in claim 5 wherein the multiplier logic includes the second control signal X₁ generation logic defined by the truth table:

space="preserve" listing-type="tabular">______________________________________ X.sub.1 C.sub.1 (d) C.sub.2 (d) C.sub.1 (d) C.sub.2 (d) C.sub.1 (d) C.sub.2 (d) C.sub.1 (d) C.sub.2 (d) C.sub.1 C.sub.2 0 0 0 1 1 0 1 1 ______________________________________ 0 0 1 0 X 1 0 1 0 0 X 0 1 0 X X X X 1 1 1 0 X 1 ______________________________________

9. The direct conversion receiver for delay-and-correlate transmitted reference spread spectrum signaling recited in claim 8 wherein said second control signal X₁ generation logic comprises:

a first Exclusive NOR gate for receiving as input signals C₁ and C₂ and generating an output signal C₁ ·

C₂ +C₁ ·

C₂ ;

a second Exclusive NOR gate for receiving as input signals C₁ (d) and C₂ (d) and for generating as an output signal C₁ (d)·

C₂ (d)+C₁ (d)·

C₂ (d); and

an AND gate for receiving the output signals of the first and second Exclusive NOR gate and for generating the output signal X₁.

10. A delay-and-correlate transmitted reference spread spectrum communications system comprising:

a transmitter including

a sequence generator for generating a spreading signal,

an Exclusive OR gate for receiving a data input and said spreading signal,

a first delay means coupled to an output of the Exclusive OR gate for generating a first delayed signal,

a summer for combining said spreading signal with said first delayed signal, and

an RF transmitter for transmitting a combined output signal from the summer; and

a receiver including

means for converting a received direct sequence spread spectrum signal having a predetermined chipping rate to a baseband signal,

an analog-to-digital converter for sampling the baseband signal at a rate greater than said chipping rate,

a second delay means coupled to the output of the analog-to-digital converter for generating a delayed signal,

multiplier logic for receiving output signals from said analog-to-digital converter and said second delay means and for generating control output signals, and

a counter responsive to said control output signals for incrementing or decrementing a count or recycling.

11. The delay-and-correlate transmitted reference spread spectrum communications system recited in claim 10 wherein said first and second delay means comprise first and second shift registers, respectively, having substantially the same delays.

12. The delay-and-correlate transmitted reference spread spectrum communications system recited in claim 11 wherein said analog-to-digital converter comprises a high comparator and a low comparator, for comparing the baseband signal to high and low thresholds, respectively.