Fully integrated data receiver and method for receiving on/off keyed AM/PDSK modulated signals

• US 5,774,502 A
• Filed: 11/19/1996
• Issued: 06/30/1998
• Est. Priority Date: 11/19/1996
• Status: Expired due to Term

• Current Assignee: Benhov GmbH, LLC (Intellectual Ventures LLC)
• Original Assignee: Harris Corporation (L3Harris Technologies, Inc.)
• Inventors: Nadler, Alexander J., Darby, Albert D. Jr., Belcher, Donald K.
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): Deppe, Betsy L.
• Application Number:
  US08/752,028
• Time in Patent Office: 588 Days
• Field of Search: 375/269, 375/283, 375/309, 375/300, 375/308, 375/310, 375/311, 375/315, 375/320, 375/330, 375/324, 375/316, 375/340, 375/259, 455/334, 455/337
• US Class Current: 375/283
• CPC Class Codes: H04L 27/389 with separate demodulation for the phase and amplitude components

Abstract

A data transmission system in which an on/off keyed (OOK) AM/DPSK modulated data signal with an on/off ratio exceeding about 80 dB which has been modulated on a carrier is received at a compact, easily fabricated and battery powered data receiver which operates without automatic gain control and which includes a double loop antenna (diameter of about two inches) with a trimmer capacitor center tapped to the antenna for providing a conjugate impedance match between the antenna and a low noise amplifier. In the receiver, a square-law detection AM demodulator for demodulating the amplified signal is in a bipolar silicon IC, and a DPSK data detector for decoding the demodulated signal is in a separate digital CMOS IC.

Claims

1. A data transmission system comprising a transmitter for transmitting an on/off keyed (OOK) AM/DPSK modulated data signal with an on/off ratio exceeding about 60 dB which has been modulated on a carrier;

and a compact data receiver which operates without automatic gain control comprising,

an antenna comprising a double loop of antenna wire, the loop being less than about three inches in diameter, and a trimmer capacitor which is connected to a center of said wire for providing a conjugate impedance match between said antenna and a low noise amplifier connected thereto;

a square-law detection AM demodulator for demodulating the amplified signal from said low noise amplifier; and

a DPSK data detector circuit for digitally decoding the demodulated signal in order to provide the data signal as an output.

2. The system of claim 1, said receiver further comprising a bipolar silicon integrated circuit having therein said low noise amplifier and said square-law detection AM demodulator.

3. The system of claim 2, said receiver further comprising a digital CMOS integrated circuit having therein said DPSK data detector circuit which comprises delay means for delaying data in the demodulated signal by one bit and a multiplier for decoding the demodulated signal by multiplying the delayed signal times the undelayed demodulated signal.

4. The system of claim 1 wherein said data signal has a frequency of about 300 Hz, said on/off keying is at about a 1.2 KHz rate, and said carrier has a frequency of about 49 MHz.

5. The system of claim 1 wherein said transmitter provides an on/off ratio exceeding about 80 dB.

6. A data communication method comprising the steps of:

(a) DPSK modulating an input data signal;

(b) on/off keying the DPSK modulated signal at a first AM rate with an on/off ratio of at least 60 dB, to produce an OOK AM/DPSK signal;

(b) modulating the OOK AM/DPSK signal onto a carrier;

(c) transmitting the modulated carrier;

(d) providing a conjugate impedance match between a double loop wire antenna receiving the transmitted signal and a low noise amplifier connected thereto, the antenna being center tapped to a trimmer capacitor for impedance matching;

(e) demodulating the signal from the low noise amplifier with a square-law detection AM demodulator in a bipolar silicon integrated circuit; and

(f) decoding the demodulated signal with DPSK data detector circuit in a digital CMOS integrated circuit which delays data in the demodulated signal by one bit and multiplies the delayed data times the undelayed demodulated signal.

7. The method of claim 6 wherein the demodulating step further comprises the step of mixing the signal from the low noise amplifier with a first oscillator signal to provide a intermediate frequency output signal to the square-law detection AM demodulator.

8. The method of claim 7 wherein the decoding step further comprises the step of switchably connecting the square-law detection AM demodulator to a delay with a second oscillator.

9. The method of claim 8 where the data signal has a frequency of about 300 Hz, the first AM rate is about 1.2 KHz, the carrier has a frequency of about 49 MHz, and the intermediate frequency is about 20 KHz.

10. The method of claim 9 wherein the first oscillator operates at about 49 MHz and the second oscillator operates at about 72 KHz and has an output divided by 4.

11. A data receiver comprising:

an antenna comprising a double loop of antenna wire center tapped to a trimmer capacitor, said antenna for receiving an on/off keyed (OOK) AM/DPSK modulated several hundred Hertz data signal with an on/off ratio exceeding about 60 dB which has been modulated on a multi-megaHertz carrier, and for providing a conjugate impedance match between said antenna and a low noise amplifier connected thereto;

an AM demodulator circuit comprising a bipolar silicon integrated circuit having therein said low noise amplifier for amplifying the signal from said antenna and a square-law detection AM demodulator for demodulating the amplified signal; and

a DPSK data detector circuit comprising a digital CMOS integrated circuit having therein delay means for delaying data in the demodulated signal by one bit and a multiplier for decoding the demodulated signal by multiplying the delayed signal times the undelayed demodulated signal, said data detector circuit for providing the several hundred Hertz data signal as an output.

12. The receiver of claim 11 wherein said bipolar silicon integrated circuit further comprises a mixer connected to said low noise amplifier and a first oscillator connected to said mixer, said mixer for providing a multi-kiloHertz, intermediate frequency output signal to said square-law detection AM demodulator.

13. The receiver of claim 12 wherein said digital CMOS integrated circuit further comprises a switch for switchably connecting said square-law detection AM demodulator to said delay means, and a second oscillator for operating said switch.

14. The receiver of claim 13 wherein said data signal has a frequency of about 300 Hz, said on/off keying is at a 1.2 KHz rate, said carrier has a frequency of about 49 MHz, and said intermediate frequency is about 20 KHz.

15. The receiver of claim 14 wherein said first oscillator operates at about 49 MHz and said second oscillator operates at about 72 KHz and has an output divided by 4.

16. The receiver of claim 11 further comprising a battery for powering the receiver.

17. The receiver of claim 11 wherein said double loop of antenna wire has a diameter of about two inches.

18. A data transmission system comprising a transmitter for transmitting an on/off keyed (OOK) AM/DPSK modulated data signal which has been modulated on a carrier;

and a compact data receiver which operates without automatic gain control comprising,

an antenna comprising a double loop of antenna wire and a trimmer capacitor which is connected to a center of said wire for providing a conjugate impedance match between said antenna and a low noise amplifier connected thereto;

a square-law detection AM demodulator for demodulating the amplified signal from said low noise amplifier; and

a DPSK data detector circuit for digitally decoding the demodulated signal in order to provide the data signal as an output.

19. The system of claim 18, said receiver further comprising a bipolar silicon integrated circuit having therein said low noise amplifier and said square-law detection AM demodulator.

20. The system of claim 19, said receiver further comprising a digital CMOS integrated circuit having therein said DPSK data detector circuit which comprises delay means for delaying data in the demodulated signal by one bit and a multiplier for decoding the demodulated signal by multiplying the delayed signal times the undelayed demodulated signal.

21. The system of claim 18 wherein said on/off keying is at a rate four times that of the said data signal frequency.

22. The system of claim 18 wherein said transmitter provides an on/off ratio exceeding 60 dB.