Method and apparatus for enhancing security in and discouraging theft of VLSI and ULSI devices

• US 5,774,545 A
• Filed: 03/28/1996
• Issued: 06/30/1998
• Est. Priority Date: 03/28/1996
• Status: Expired due to Term

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Lucent Technologies, Inc. (Nokia Corporation)
• Inventors: Raghavachari, Partha
• Primary Examiner(s): CANGIALOSI, SALVATORE A
• Application Number:
  US08/623,271
• Time in Patent Office: 824 Days
• Field of Search: 380/4, 380/23, 365/185.33
• US Class Current: 713/189
• CPC Class Codes: G01R 31/31719 Security aspects, e.g. preventing unauthorised access during test
• CPC Class Codes: G01R 31/318533 using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
• CPC Class Codes: G06F 11/006 Identification G06F11/2289 takes precedence
• CPC Class Codes: G06F 21/575 Secure boot
• CPC Class Codes: G06F 21/88 Detecting or preventing theft or loss
• CPC Class Codes: G06F 2207/7219 Countermeasures against side channel or fault attacks
• CPC Class Codes: G06F 2221/2103 Challenge-response

Abstract

VLSI and ULSI devices like microprocessors and DRAM devices are prone to large scale theft from factories and warehouses. A proposed method of reducing the theft incorporates a small amount of non-volatile flash memory in these devices. The flash memory contains password, device serial number and user identification information. On power-up, the device initiates an encrypted password verification session through a standard interface. If the user supplied password fails, the device'"'"'s operational ports (any data or control output buses) are tri-stated, thus making the device unusable. The device serial number and user identification information are useful in determining ownership of stolen devices when recovered.

Claims

1. A large scale integrated device having a core functional circuit and at least one output port, said device comprising:

a security mechanism;

a controller to control the operation of the security mechanism;

a boundary scan port electrically coupled to said controller, said boundary scan port providing an interface between the security mechanism and an external medium;

a flash memory electrically coupled to said controller, said flash memory providing the security mechanism with non-volatile storage of predetermined information and data;

a set of security registers for providing functional support to said controller, said security registers electrically coupled to said flash memory, said controller and said boundary scan port; and

tristate control logic for providing said controller with functional control over the core functional circuit and the output ports of the large scale integrated device, said tristate logic control electrically coupled to said controller, the core functional circuit and output ports of the device.

2. The device of claim 1 wherein said controller includes combinational logic and state machine flip-flops to interpret commands sent by said external medium, manage said flash memory and said security registers, verify passwords for unlocking the device, supply said external medium with said predetermined data, and control the output ports of the core functional circuit through said tristate logic.

3. The device of claim 1 wherein said flash memory provides 128 bytes of memory to store said predetermined information and data, each said byte being eight bits wide and having a separate location address, wherein the first byte is location address 0 and the last byte is location address 127.

4. The device of claim 3 wherein said predetermined information and data includes user identification information, a password, a device serial number, a random security challenge, security session status information, and failure information.

5. The device of claim 4 wherein said security status information is stored in location address 0, said failure information is stored in location addresses 1 and 2, said user identification is stored in location addresses 3-47, said password is stored in location addresses 48-63, said serial number is stored in location addresses 64-95, and said random security challenge is stored in location addresses 96-127.

6. The device of claim 4 wherein said random security challenge is a test, wherein said test requires said external medium to return a value at the beginning of each power-up of the device to unlock the device.

7. The device of claim 1 wherein said security registers include a security status register, a security command register, a failure threshold register, a failure count register, a device password register, a random challenge register, and a temporary data register.

8. The device of claim 1 wherein said boundary scan port further comprises a test access port controller, an instruction register, an instruction decoder, a device bypass register and a boundary scan register.

9. A built-in security mechanism for a large scale integrated device, the device having a core functional circuit and output ports, the security mechanism comprising:

a controller to control the operation of the security mechanism;

a boundary scan port electrically coupled to said controller, said boundary scan port providing an interface between the security mechanism and an external medium;

a flash memory electrically coupled to said controller, said flash memory providing the security mechanism with non-volatile storage of predetermined information and data;

a set of security registers for providing functional support to said controller, said security registers electrically coupled to said flash memory, said controller and said boundary scan port; and

tristate control logic for providing said controller with functional control over the core functional circuit and the output ports of the large scale integrated device, said tristate logic control electrically coupled to said controller and the core functional circuit and output ports of the device to prevent unauthorized use thereof.

10. The device of claim 9 wherein said controller includes combinational logic and state machine flip-flops to interpret commands sent by said external medium, manage said flash memory and said security registers, verify passwords for unlocking the device, supply said external medium with said predetermined data, and control the output ports of the core functional circuit through said tristate logic.

11. The device of claim 10 wherein said flash memory provides 128 bytes of memory to store said predetermined information and data, each said byte being eight bits wide and having a separate location address, wherein the first byte is location address 0 and the last byte is location address 127.

12. The device of claim 11 wherein said predetermined information and data includes user identification information, a password, a device serial number, a random security challenge, security session status information, and failure information.

13. The device of claim 12 wherein said security status information is stored in location address 0, said failure information is stored in location addresses 1 and 2, said user identification is stored in location addresses 3-47, said password is stored in location addresses 48-63, said serial number is stored in location addresses 64-95, and said random security challenge is stored in location addresses 96-127.

14. The device of claim 12 wherein said random security challenge is a test, wherein said test requires said external medium to return a value at the beginning of each power-up of the device to unlock the device.

15. The device of claim 9 wherein said security registers include a security status register, a security command register, a failure threshold register, a failure count register, a device password register, a random challenge register, and a temporary data register.

16. The device of claim 15 wherein said boundary scan port further comprises a test access port controller, an instruction register, an instruction decoder, a device bypass register and a boundary scan register.

17. A method of protecting large scale integrated devices from theft, the large scale integrated devices having a core functional circuit and output ports, the method comprising the steps of:

entering into a security session between a security mechanism and an external medium to protect unauthorized access to the core functional circuit and the output ports from said external medium; and

controlling access to the core functional circuit and the output ports through tristate control logic by verifying a requested password from said external medium.

18. The method of claim 17 wherein said security session comprises the steps of:

a. requesting the external medium to return a password upon each power-up of the device;

b. comparing said returned password to a preprogrammed password in said security mechanism to determine if a password match exists therebetween.

c. providing said external medium access to the device if said password match exists.

19. The method of claim 17 wherein said security session comprises the steps of:

a. requesting the external medium to return a random challenge value upon each power-up of the device;

b. comparing said returned random challenge value to a random challenge value calculated by said security mechanism to determine if a challenge value match exists therebetween;

c. providing said external medium access to the device if said challenge value match exists.

20. The method of claim 19 wherein said random challenge value is a value calculated by both said external medium and said security mechanism from a set of random variables.

21. The method of claim 17 wherein said security session comprises the steps of:

a. requesting the external medium to return a password and a random challenge value upon each power-up of the device;

b. comparing said returned random challenge value to a random challenge value calculated by said security mechanism to determine if a challenge value match exists therebetween;

c. comparing said returned password to a preprogrammed password in said security mechanism to determine if a password match exists therebetween;

d. providing said external medium access to the device if both said challenge value match and said password match exist.

22. The method of claim 17 wherein said security mechanism enters into a device serial number change session if said external medium passes said security session.

23. The method of claim 17 wherein said security mechanism enters into a password change session if said external medium passes said security session.

24. The method of claim 17 wherein said security mechanism enters into a device serial number read session if said external medium passes said security session.

25. The method of claim 17 wherein said security mechanism enters into a failure threshold change session if said external medium passes said security session.