Integrated circuit having function blocks operating in response to clock signals

• US 5,774,702 A
• Filed: 11/22/1995
• Issued: 06/30/1998
• Est. Priority Date: 11/22/1994
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi, Ltd.
• Inventors: Ishibashi, Kenichi, Mitsuishi, Naoki, Hashimura, Koichi
• Primary Examiner(s): Heckler, Thomas M.
• Application Number:
  US08/561,728
• Time in Patent Office: 951 Days
• Field of Search: 395/556, 395/559
• US Class Current: 713/501
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency

Abstract

A semiconductor integrated circuit comprising a clock pulse generator, peripheral function blocks and bus master modules. The peripheral function blocks are commonly supplied with a first system clock signal of a constant frequency generated on the basis of the output from the clock pulse generator. The bus master modules are fed with a second system clock signal generated on the basis of the pulse generator output. The frequency of the second system clock signal is variable and lower than that of the first system clock signal. The function blocks supplied with the first system clock signal are connected to a data bus separate from the one connected to the function blocks fed with the second system clock signal.

Claims

1. A semiconductor integrated circuit comprising:

A first function block opening in accordance with a first supplied system clock signal;

a plurality of second function blocks operating in accordance with a second supplied system clock signal;

a clock control circuit receiving a predetermined clock signal and including a clock signal generation circuit operating with a variable frequency division ratio and generating a first system clock signal by dividing the predetermined clock signal;

a first clock signal line for supplying the first system clock signal as the first supplied system clock signal to the first function block; and

a second clock signal line for commonly supplying the second function blocks with a second system clock signal having a second frequency as the second supplied system clock signal, the second system clock signal being generated on the basis of the predetermined clock signal.

2. A semiconductor integrated circuit according to claim 1, further comprising a bus connected to the first function block and to the second function blocks, wherein the first function block operates as a bus master.

3. A semiconductor integrated circuit according to claim 2, wherein the second function blocks operate as bus slaves.

4. A semiconductor integrated circuit according to claim 3, wherein the clock control circuit includes a register for retaining information for determining the frequency division ratio, and wherein the first function block loads the information into the register.

5. A semiconductor integrated circuit according to claim 3, wherein the bus includes a first internal data bus to which the first function block is connected and a second internal data bus to which the second function blocks are connected, and wherein the semiconductor integrated circuit further comprises a bus controller for connecting the first internal data bus to the second internal data bus when the bus master accesses one of the bus slaves.

6. A semiconductor integrated circuit according to claim 5, further comprising holding circuits connected to the second internal data bus, the holding circuits retaining status of the second internal data bus when an output of one of the second function blocks is in a high impedance state, the holding circuits further allowing the status to be changed in accordance with data to be either written to or read from the second internal data bus by one of the second function blocks.

7. A semiconductor integrated circuit according to claim 3,

wherein the first function block includes a non-overlapping signal generation circuit for generating non-overlapping first two-phase clock signals on the basis of the first system clock signal;

wherein the second function blocks include a non-overlapping signal generation circuit for generating non-overlapping second two-phase clock signals on the basis of the second system clock signal; and

wherein the first two-phase clock signals and the second two-phase clock signals have phases with a defined phase relationship therebetween, wherein, data to be fed to the first function block is changed in synchronism with the defined phase relationship.

8. A semiconductor integrated circuit according to claim 3,

wherein the first function block includes a non-overlapping signal generation circuit for generating non-overlapping first two-phase clock signals on the basis of the first system clock signal;

wherein the second function blocks include a non-overlapping signal generation circuit for generating non-overlapping second two-phase clock signals on the basis of the second system clock signal; and

wherein the low-level periods of a first one of the first two-phase clock signals coincide with those of a first one of the second two-phase clock signals, and the high-level periods of a second one of the first two-phase clock signals coincide with those of a second one of the second two-phase clock signals.

9. A semiconductor integrated circuit according to claim 3, further comprising:

external terminals;

an output circuit connected interposingly between the external terminals and the clock signal lines, the output circuit outputting clock signals of the clock signal lines selectively to the external terminals; and

a logic circuit for receiving the first system clock signal and the second system clock signal and for supplying either the first system clock signal or the second system clock signal to the clock signal lines when either the first system clock signal or the second system clock signal is to be output from the external terminals, the logic circuit setting fixedly the clock signal lines to a predetermined potential when the output circuit disables the output of clock signals to the external terminals.

10. A semiconductor integrated circuit comprising:

a plurality of function blocks having a clock signal generation circuit coupled to receive predetermined clocks and for generating internal clock signals of a plurality of phases and operating in accordance with the internal clock signals; and

register means provided in common to the function blocks, the register means retaining control information corresponding to each of the function blocks for controlling selection of the corresponding function block;

wherein the clock signal generation circuit includes a control circuit for selectively disabling the generation of the internal clock signals and outputting a signal of a predetermined state in accordance with the corresponding control information.

11. A semiconductor integrated circuit according to claim 10, wherein each function block includes an internal timing signal generation circuit for generating internal timing signals on the basis of the internal clock signals of a plurality of phases when the function block is selected, the internal timing signal generation circuit including a control circuit for limiting the internal timing signals to a predetermined state when the function block is unselected.

12. A semiconductor integrated circuit according to claim 11,

wherein the internal timing signals are non-overlapping two-phase timing signals;

and

wherein the function blocks each include a dynamic circuit and static circuit, the dynamic circuit operating dynamically in accordance with a first one of the two-phase timing signals, the static circuit being connected serially to the dynamic circuit and operating statically in accordance with a second one of the two-phase timing signals.

13. A semiconductor integrated circuit comprising:

a first function block for performing first processing and exception handling in accordance with a first system clock signal;

an event detection circuit for outputting, upon detection of an event, a request signal requesting the first function block to execute exception handling;

second function blocks for generating events; and

a control circuit for changing the frequency of the first system clock signal and setting the first system clock signal to a predetermined frequency in response to the request signal.

14. A semiconductor integrated circuit according to claim 13, wherein the control circuit includes;

register means having a first and a second storage area; and

a selector for receiving a plurality of clock signals of different frequencies including the predetermined frequency, the selector outputting the clock signal of the predetermined frequency as the first system clock signal when the first storage area of the register means is placed in a first state, the selector further outputting one of the plurality of clock signals as the first system clock signal in accordance with information held in the second storage area when the first storage area of the register means is placed in a second state.

15. A semiconductor integrated circuit according to claim 14, wherein the first function block includes a central processing unit for placing the first storage area of the register means in the second state upon returning from the exception handling.

16. A semiconductor integrated circuit according to claim 14, wherein the first function block comprises a data transfer controller for outputting an end signal when the exception handling is completed, the end signal causing the first storage area of the register means to be placed in the second state.

17. A semiconductor integrated circuit according to claim 13,

wherein each of the second function blocks includes a clock signal generation circuit for generating internal clock signals on the basis of a second system clock signal having a predetermined frequency, the second function blocks operating in accordance with the internal clock signals;

and

wherein the semiconductor integrated circuit further comprises second register means for retaining control information for controlling the clock signal generation circuit generating the internal clock signals, the second register means being loaded with information for inhibiting the clock signal generation circuit from generating the internal clock signals in response to the detection of an event by the event detection circuit.

18. A semiconductor integrated circuit according to claim 13, wherein the event detection circuit operates in accordance with the first system clock signal.

19. A semiconductor integrated circuit comprising:

a central processing unit wherein in response to a request for exception handling, the central processing unit retrieves information from a vector area in a memory corresponding to the requested exception handling, the central processing unit operating in accordance with a first system clock signal;

an event detection circuit for detecting an event and outputting an exception handling request to the central processing unit;

first register means for retaining information for designating the frequency of the first system clock signal;

peripheral circuits each including a clock signal generation circuit for generating internal clock signals on the basis of a second system clock signal, the peripheral circuits operating in accordance with the internal clock signals; and

second register means for retaining information for controlling the clock signal generation circuit generating the internal clock signals in each of the peripheral circuits;

wherein the information to be loaded into the first and second register means upon request for exception handling is retained in an area in the memory corresponding to the vector area, wherein the information is retrieved from the area in the memory corresponding to the vector area and loaded into the first and the second register means when exception handling is requested.

20. A semiconductor integrated circuit according to claim 19, wherein the central processing unit saves into a stack area of the memory information retained in the first and the second register means prior to the exception handling request, wherein after the exception handling request the information is retrieved from the area in the memory corresponding to the vector area and loaded into the first and said second register means.

21. A semiconductor integrated circuit according to claim 19, wherein the event detection circuit operates in accordance with the first system clock signal.

22. A semiconductor integrated circuit having a plurality of function blocks operating in accordance with a system clock signal, the semiconductor integrated circuit comprising:

a clock signal generation circuit generating the clock signal; and

a pre-scaler generating a first clock signal by dividing the clock signal by a frequency division ratio greater than a first frequency division ratio, the first clock signal being fed via clock signal lines to at least two function blocks within the plurality of function blocks;

wherein one or more of the plurality of function blocks include a frequency divider for dividing the clock signal by a frequency division ratio smaller than the first frequency division ratio.

23. A semiconductor integrated circuit, comprising:

a CPU operating in response to a first clock signal;

a plurality of peripheral modules operating in response to a second clock signal commonly supplied to each of the plurality of peripheral modules; and

a clock controller receiving a predetermined clock signal, wherein the clock controller variably divides the predetermined clock signal to generate the first clock signal having a variable frequency in response to control information in a register, wherein the clock controller generates the second clock signal having a frequency based on the predetermined clock signal;

wherein the frequency of the first clock signal is varied while the frequency of the second clock signal is not varied.

24. The semiconductor integrated circuit of claim 23, wherein the control information in the register is changed by the CPU.

25. The semiconductor integrated circuit of claim 23:

wherein the CPU includes a non-overlapping signal generation circuit for generating non-overlapping first two-phase clock signals on the basis of the first clock signal;

wherein the plurality of peripheral modules each include a non-overlapping signal generation circuit for generating non-overlapping second two-phase clock signals on the basis of the second clock signal; and

wherein the first two-phase clock signals and the second two-phase clock signals have phases with a defined phase relationship therebetween, wherein, data to be fed to the CPU is changed in synchronism with the defined phase relationship.

26. The semiconductor integrated circuit of claim 23, wherein each peripheral module includes an internal timing signal generation circuit generating internal timing signals of a plurality of phases on the basis of the second clock signal when the peripheral module is selected, wherein the internal timing signal generation circuit includes a control circuit for limiting the internal timing signals to a predetermined state when the peripheral module is unselected.

27. The semiconductor integrated circuit of claim 26,

wherein the internal timing signals comprise non-overlapping two-phase timing signals;

and

wherein each peripheral module includes a dynamic circuit and a static circuit, wherein the dynamic circuit operates dynamically in accordance with a first one of the two-phase timing signals, wherein the static circuit is connected serially to the dynamic circuit and operates statically in accordance with a second one of the two-phase timing signals.

28. The semiconductor integrated circuit of claim 23, wherein the CPU performs first processing and exception handling in accordance with the first clock signal, the semiconductor integrated circuit further comprising an event detection circuit for outputting, upon detection of an event, a request signal requesting the CPU to execute exception handling and a control circuit for varying the frequency of the first clock signal in response to the request signal.

29. The semiconductor integrated circuit of claim 28, wherein the first clock signal has a first frequency when the CPU perform first processing, wherein, in response to the event detection, the control information in the register is changed to control information for the detected event, wherein the first clock signal has a second frequency during exception handling, wherein, in response to completion of the exception handling, the control information is restored in the register, wherein the first clock signal has the first frequency after completion of the exception handling.