Low distortion switch

• US 5,774,792 A
• Filed: 08/11/1995
• Issued: 06/30/1998
• Est. Priority Date: 08/29/1994
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi, Ltd.
• Inventors: Kitayama, Taro, Tanaka, Satoshi, Yamane, Masao, Okamoto, Tatsuto
• Primary Examiner(s): Pham, Chi H.
• Assistant Examiner(s): ARTHUR JEANGLAUDE, GERTRUDE
• Application Number:
  US08/514,194
• Time in Patent Office: 1,054 Days
• Field of Search: 455/50.1, 455/78, 455/82, 455/83, 455/501, 333/103, 333/104, 327/408, 327/430, 327/435, 327/436, 257/275
• US Class Current: 455/78
• CPC Class Codes: H03K 17/063 in field-effect transistor switches
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00

Abstract

This invention is intended to realize a high frequency switch with a low distortion characteristic. In an SPDT switch consisting of a plurality of FETs, the FET on the receiver side through which a received signal passes and the shunt FET on the transmitter side are each formed of series-connected FETs, and a capacitor is connected between the first gate and the source and between the second gate and the drain. An inductance is connected in parallel with a series connection of FETs. This easily realizes a high frequency switch having a low voltage and a low distortion characteristic. The 1 dB compression level, an index of input-output characteristic, can be improved more than 5 dB over the conventional SPDT switch at an input level.

Claims

1. An SPDT switch (single-pole double-throw switch) used in a transceiver for switching between a transmitting mode and a receiving mode, comprising:

a first signal node for outputting a received signal to a receiver;

a second signal node for receiving a received signal from an antenna and outputting a sending signal to the antenna;

a third signal node for receiving a sending signal of high frequency and large power from a transmitter;

a first switch having a first FET provided between a ground level and the first signal node;

a second switch having a second FET and a third FET connected in series between the first signal node and the second signal node;

a third switch having a fourth FET provided between the second signal node and the third signal node; and

a fourth switch having a fifth FET and a sixth FET connected in series between the third signal node and the ground level;

wherein the SPDT switch introduces the received signal from the antenna to the receiver by controlling a DC bias applied to gate metals of each FET, turning on the second and fourth switches and turning off the first and third switches, and introduces the sending signal from the transmitter to the antenna by turning off the second and fourth switches and turning on the first and third switches;

wherein the second switch has a source node of the second FET connected to the first signal node, a source node of the third FET connected to the second signal node, and drains of the second FET and the third FET connected together at a first connecting point;

wherein the fourth switch has a source node of the fifth FET connected to the third signal node, a source node of the sixth FET connected to the ground level, and drains of the fifth FET and the sixth FET connected together at a second connecting point;

wherein a first distance between the first connecting point and a gate of the second FET is larger than or equal to a second distance between the source node of the second FET and the gate of the second FET, the first distance being approximately equal to a distance between the first connecting point and a gate of the third FET, and the second distance being approximately equal to a distance between the source node of the third FET and the gate of the third FET; and

wherein a third distance between the second connecting point and a gate of the fifth FET is larger than or equal to a fourth distance between the source node of the sixth FET and the gate of the sixth FET, the third distance being approximately equal to a distance between the second connecting point and a gate of the sixth FET, and the fourth distance being approximately equal to a distance between the source node of the sixth FET and the gate of the sixth FET.

2. An SPDT switch used in a transceiver for switching between a transmitting mode and a receiving mode, according to claim 1, wherein the second switch has two capacitors connected between the source node and the gate metal of each of the second and third FETs forming the second switch, and the fourth switch has two capacitors connected between the source node and the gate metal of each of the fifth and sixth FETs forming the fourth switch.

3. An SPDT switch used in a transceiver for switching between a transmitting mode and a receiving mode, according to claim 2, wherein each of the capacitors is formed on source contact nodes by forming a dielectric contact film between a source metal and a gate metal.

4. An SPDT switch used in a transceiver for switching between a transmitting mode and a receiving mode, according to claim 2, further comprising:

an inductor connected in parallel with the second switch; and

an inductor connected in parallel with the third switch.

5. An SPDT switch (single-pole double-throw switch) used in a transceiver for switching between a transmitting mode and a receiving mode, comprising:

a first signal node for outputting a received signal to a receiver;

a second signal node for receiving a received signal from an antenna and outputting a sending signal to the antenna;

a third signal node for receiving a sending signal of high frequency and large power from a transmitter;

a first switch having an FET provided between a ground level and the first signal node, the FET having a gate metal;

a second switch having a first dual gate FET, which effectively includes drain nodes of two FETs being connected in a series connection of the two FETs, provided between the first signal node and the second signal node, the first dual gate FET having two gate metals;

a third switch having an FET between the second signal node and the third signal node, the FET having one gate metal; and

a fourth switch having a second dual gate FET, which effectively includes two drain nodes of two FETs being connected in a series connection of the two FETs, between the third signal node and the ground level, the second dual gate FET having two gate metals;

wherein the SPDT switch introduces the received signal from the antenna to the receiver by controlling a DC bias applied to gate metals of each FET, turning on the second and fourth switches and turning off the first and third switches, and introduces the sending signal from the transmitter to the antenna by turning off the second and fourth switches and turning on the first and third switches; and

wherein the second switch and the fourth switch are formed in such a way that the two gate metals of the first and second dual gate FETs are arranged parallelly on a common channel region, that two source nodes of the first and second dual gate FETs are arranged on a contact region on the outside of the channel region, and that the distance between the gate metals is longer than or equal to the distance between the adjacent gate metal and source node.

6. An SPDT switch used in a transceiver for switching between a transmitting mode and a receiving mode, according to claim 5, wherein the second switch has two capacitors connected between the adjacent source node and gate metal of the first dual gate FET, and the fourth switch has two capacitors connected between the adjacent source node and drain node of the second dual gate FET.

7. An SPDT switch used in a transceiver for switching between a transmitting mode and a receiving mode, according to claim 6, wherein each of the capacitors is formed on source contact nodes by forming a dielectric contact film between a source metal and a gate metal.

8. An SPDT switch used in a transceiver for switching between a transmitting mode and a receiving mode, according to claim 6, further comprising:

an inductor connected in parallel with the second switch; and

an inductor connected in parallel with the third switch.

9. An SPDT switch (single-pole double-throw switch) used in a transceiver for switching between a transmitting mode and a receiving mode, comprising:

a first signal node for outputting a received signal to a receiver;

a second signal node for receiving a received signal from an antenna and outputting a sending signal to the antenna;

a third signal node for receiving a sending signal of high frequency and large power from a transmitter;

a first switch having an FET provided between a ground level and the first signal node, the FET having a gate metal;

a second switch having a first dual rate FET, which effectively includes drain nodes of two FETs being connected in a series connection of the two FETs, provided between the first signal node and the second signal node, the first dual rate FET having two gate metals;

a third switch having an FET between the second signal node and the third signal node, the FET having one gate metal; and

a fourth switch having a second dual gate FET, which effectively includes drain nodes of two FETs being connected in a series connection of the two FETs, between the third signal node and the ground level, the second dual gate FET having two gate metals;

wherein the SPDT switch introduces the received signal from the antenna to the receiver by controlling a DC bias applied to gate metals of each FET, turning on the second and fourth switches and turning off the first and third switches, and introduces the sending signal from the transmitter to the antenna by turning off the second and fourth switches and turning on the first and third switches; and

wherein the second switch and the fourth switch are formed in such a way that the two gate metals of the first and second dual gate FETs are arranged parallelly on a channel region on the outside of an ion implantation, that two source nodes of the first and second dual gate FETs are arranged on a contact region on the outside of the channel region, that the distance between one of the gate metals and the ion implantation is longer than the distance between the one gate metal and one of the source nodes adjacent to it and that the distance between the other gate metal and the ion implantation is longer than the distance between the other gate metal and the other source node adjacent to it.

10. An SPDT switch used in a transceiver for switching between a transmitting mode and a receiving mode, according to claim 9, wherein the second switch has two capacitors connected between the adjacent source node and gate metal of the first dual gate FET, and the fourth switch has two capacitors connected between the adjacent source node and drain node of the second dual gate FET.

11. An SPDT switch used in a transceiver for switching between a transmitting mode and a receiving mode, according to claim 10, wherein each of the capacitors is formed on source contact nodes by forming a dielectric contact film between a source metal and a gate metal.

12. An SPDT switch used in a transceiver for switching between a transmitting mode and a receiving mode, according to claim 10, further comprising:

an inductor connected in parallel with the second switch; and

an inductor connected in parallel with the third switch.