Method of encapsulating a semiconductor package

• US 5,776,796 A
• Filed: 10/07/1996
• Issued: 07/07/1998
• Est. Priority Date: 05/19/1994
• Status: Expired due to Term

• Current Assignee: Tessera, Inc. (Adeia, Inc.)
• Original Assignee: Tessera, Inc. (Adeia, Inc.)
• Inventors: Mitchell, Craig S., Karavakis, Konstantine, Fjelstad, Joseph, Smith, John W., Distefano, Thomas H.
• Primary Examiner(s): PICARDAT, KEVIN M
• Application Number:
  US08/726,697
• Time in Patent Office: 638 Days
• Field of Search: 437/209, 437/211, 437/212, 437/214, 437/215, 437/216, 437/219
• US Class Current: 438/106
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2224/11003 for holding or transferring the bump preform
• CPC Class Codes: H01L 2224/2612 Auxiliary members for layer connectors, e.g. spacers
• CPC Class Codes: H01L 2224/83102 using surface energy, e.g. capillary forces
• CPC Class Codes: H01L 2224/86 using tape automated bonding [TAB]
• CPC Class Codes: H01L 2224/92125 the second connecting process involving a layer connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/24 solid or gel at the normal operating temperature of the device H01L23/3135 takes precedence
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/49572 consisting of thin flexible metallic tape with or without a film carrier H01L23/49503 - H01L23/49568 and H01L23/49575 - H01L23/49579 take precedence
• CPC Class Codes: H01L 24/32 of an individual layer connector
• CPC Class Codes: H01L 24/50 Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto thin flexible metallic tape with or without a film carrier H01L23/49572, flexible insulating substrates H01L23/4985, H01L23/5387
• CPC Class Codes: H01L 24/86 using tape automated bonding [TAB]
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01058 : Cerium [Ce]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/12042 : LASER

Abstract

A method of encapsulating a semiconductor device. The encapsulation method includes a semiconductor chip package assembly having a spacer layer between a top surface of a sheet-like substrate and a contact bearing surface of a semiconductor chip, wherein the substrate has conductive leads thereon, the leads being electrically connected to terminals on a first end and bonded to respective chip contacts on a second end. Typically, the spacer layer is comprised of a compliant or elastomeric material. A protective layer is attached on a bottom surface of the substrate so as to cover the terminals on the substrate. A flowable, curable encapsulant material is deposited around a periphery of the semiconductor chip after the attachment of the protective layer so as to encapsulate the leads. The encapsulant material is then cured. Typically, this encapsulation method is performed on a plurality of chip assemblies simultaneously.

Claims

1. A method of encapsulating a semiconductor device, comprising the steps of:

disposing a spacer layer between a top surface of a sheet-like substrate and a contact bearing surface of a semiconductor chip, wherein the substrate has terminals thereon and bonding windows such that conductive leads electrically connected to the terminals extend at least partially thereacross and are juxtaposed with respective chip contacts;

bonding the leads to respective chip contacts;

attaching a protective layer on a bottom surface of the substrate so as to cover the bonding windows;

depositing flowable encapsulation material around at least a portion of the periphery of the chip after attaching the protective layer so as to encapsulate the bonded leads; and

at least partially curing the encapsulation material.

2. The method as claimed in claim 1, wherein the spacer layer is comprised of a compliant material.

3. The method as claimed in claim 1, further including the step of dicing the encapsulated chip from the substrate.

4. The method as claimed in claim 3, wherein the dicing step further includes the step of creating cured encapsulant bumpers around the periphery of the chip.

5. The method as claimed in claim 3, wherein a plurality of semiconductor devices are simultaneously encapsulated.

6. The method as claimed in claim 5, wherein the dicing step singulates each semiconductor device.

7. The method as claimed in claim 6, further comprising the step of attaching the substrate to a frame prior to the depositing step so as to hold the substrate substantially taut in an area bearing the semiconductor devices thereby defining a multi-device frame assembly.

8. The method as claimed in claim 6, further comprising the step of attaching the protective layer to a frame prior to the depositing step so as to hold the substrate substantially taut in an area bearing the semiconductor devices thereby defining a multi-device frame assembly.

9. The method as claimed in claim 3, further comprising the step of removing portions of the protective layer to expose the substrate terminals wherein the terminals lie beneath the periphery of the chip.

10. The method as claimed in claim 4, further comprising the step of removing portions of the protective layer to expose the substrate terminals wherein at least some of the terminals lie outside of the periphery of the chip and are supported by the bumpers.

11. The method as claimed in claim 4, further comprising the step of attaching a membrane to the exposed surfaces of the chip and the bumpers.

12. The method as claimed in claim 2, wherein the compliant layer is comprised of a plurality of compliant pads.

13. The method as claimed in claim 12, wherein the depositing step is performed so that the encapsulant flows between the compliant pads.

14. A method of encapsulating a semiconductor device, comprising the steps of:

disposing a spacer layer between a top surface of a sheet-like substrate and a contact bearing surface of a semiconductor chip, wherein the substrate has conductive leads thereon, the leads being electrically connected to terminals on the substrate on a first end and bonded to respective chip contacts on a second end;

attaching a protective layer on a bottom surface of the substrate so as to cover the terminals;

depositing flowable encapsulation material around at least a portion of the periphery of the chip after attaching the protective layer so as to encapsulate the bonded leads; and

curing the encapsulation material.

15. The method as claimed in claim 14, wherein the spacer layer is comprised of a compliant material.

16. The method as claimed in claim 14, further including the step of dicing the encapsulated chip from the substrate.

17. The method as claimed in claim 16, wherein the dicing step further includes the step of creating cured encapsulant bumpers around the periphery of the chip.

18. The method as claimed in claim 16, wherein a plurality of semiconductor devices are simultaneously encapsulated and wherein the dicing step singulates each semiconductor device.

19. The method as claimed in claim 18, further comprising the step of attaching the substrate to a frame prior to the depositing step to hold the substrate substantially taut in an area bearing the semiconductor devices thereby defining a multi-device frame assembly.

20. The method as claimed in claim 18, further comprising the step of attaching the protective layer to a frame prior to the depositing step so as to hold the substrate substantially taut in an area bearing the semiconductor devices thereby defining a multi-device frame assembly.

21. The method as claimed in claim 16, further comprising the step of removing portions of the protective layer to expose the substrate terminals wherein the terminals lie beneath the periphery of the chip.

22. The method as claimed in claim 17, further comprising the step of removing portions of the protective layer to expose the substrate terminals wherein at least some of the terminals lie outside of the periphery of the chip and are supported by the bumpers.

23. The method as claimed in claim 17, further comprising the step of attaching a membrane to the exposed surfaces of the chip and the bumpers.

24. The method as claimed in claim 14, wherein the compliant layer is comprised of a plurality of compliant pads.

25. The method as claimed in claim 24, wherein the depositing step is performed so that the encapsulant flows between the compliant pads.

26. A method of encapsulating a semiconductor device, comprising the steps of:

disposing a spacer layer between a top surface of a sheet-like substrate and a contact bearing surface of a semiconductor chip, wherein the substrate has conductive leads which are electrically connected to terminals on the substrate on a first end and bonded to respective chip contacts on a second end;

placing raised terminals atop the terminal regions;

placing the semiconductor device into a mold prior to the encapsulation step wherein the raised terminals provide a stand-off between substrate and the mold;

depositing flowable encapsulation material into the mold around a at least a portion of the periphery of the chip so as to encapsulate the leads and substrate while leaving at least a portion of the raised terminals exposed; and

removing the mold after at least a portion of the encapsulation material has been cured.

27. The method as claimed in claim 26, wherein the spacer layer is comprised of a compliant material.

28. The method as claimed in claim 26, further comprising the step of removing the raised terminals after the removal of the mold.

29. The method as claimed in claim 26, wherein a plurality of semiconductor devices are simultaneously encapsulated within the same mold.

30. The method as claimed in claim 29, further including the step of dicing the encapsulated packages after removing the mold.

31. The method as claimed in claim 29, wherein the dicing step further includes the step of creating cured encapsulant bumpers around the periphery of the chip.

32. The method as claimed in claim 31, wherein at least some of the terminals lie outside of the periphery of the chip and are supported by the bumpers.

33. The method as claimed in claim 26, wherein the compliant layer is comprised of a plurality of compliant pads.

34. The method as claimed in claim 33, wherein the depositing step is performed so that the encapsulant flows between the compliant pads.

35. A method of encapsulating a semiconductor device assembly, comprising the steps of:

providing a sheet-like, dielectric substrate having a first and second surface and an inner portion and an outer portion, the inner and outer portions being separated by at least one bonding window extending through the substrate, the substrate further having conductive terminals on at least the outer portion on the second surface of the substrate;

providing a rigid element having first and second opposite surfaces;

attaching a back surface of a semiconductor chip to the first surface of the rigid element;

disposing a first spacer layer between the first surface of the inner portion of the substrate and a contact-bearing face surface of the chip so that both the substrate and the chip are adhered thereto;

disposing a second spacer layer between the first surface of the outer portion of the substrate and the first surface of the rigid element and a contact-bearing face surface of the chip so that both the substrate and the rigid element are adhered thereto;

electrically connecting the terminals to respective chip contacts through the at least one bonding window in the substrate;

attaching a protective layer on a bottom surface of the substrate so as to cover the bonding windows;

depositing flowable encapsulation material around at least a portion of the periphery of the chip after attaching the protective layer so as to encapsulate the bonded leads; and

at least partially curing the encapsulation material.

36. The method as claimed in claim 35, wherein the first and second spacer layers are comprised of a compliant material.

37. The method as claimed in claim 36, wherein the substrate further having conductive terminals on both the inner and outer portions on the second surface of the substrate.

38. The method as claimed in claim 35, wherein the bonding window completely separates the inner and outer portions of the substrate from each other.

39. The method as claimed in claim 36, further including the step of dicing the encapsulated chip assembly from the substrate.

40. The method as claimed in claim 39, wherein the dicing step further includes the step of creating cured encapsulant bumpers around the periphery of the chip assembly.

41. The method as claimed in claim 39, wherein a plurality of semiconductor chip assemblies are simultaneously encapsulated.

42. The method as claimed in claim 41, further comprising the step of attaching the substrate to a frame prior to the depositing step so as to hold the substrate substantially taut in an area bearing the semiconductor devices thereby defining a multi-device frame assembly.

43. The method as claimed in claim 41, further comprising the step of attaching the protective layer to a frame prior to the depositing step so as to hold the substrate substantially taut in an area bearing the semiconductor devices thereby defining a multi-device frame assembly.

44. The method as claimed in claim 39, further comprising the step of removing portions of the protective layer to expose the substrate terminals.

45. The method as claimed in claim 35, wherein the first spacer layer is comprised of a plurality of compliant pads.

46. The method as claimed in claim 35, wherein the second spacer layer is comprised of a plurality of compliant pads.

47. The method as claimed in claim 45 or 46, wherein the depositing step is performed so that the encapsulant flows between the compliant pads.