Grayscale shading for liquid crystal display panels

• US 5,777,590 A
• Filed: 08/25/1995
• Issued: 07/07/1998
• Est. Priority Date: 08/25/1995
• Status: Expired due to Term

• Current Assignee: S3 Graphics Co., Ltd. (HTC Corporation)
• Original Assignee: S3 Inc. (SONICblue Incorporated)
• Inventors: Saxena, Nirmal R., Manthani, Sridhar
• Primary Examiner(s): Powell, Mark R.
• Application Number:
  US08/519,690
• Time in Patent Office: 1,047 Days
• Field of Search: 345/89, 345/148, 345/147, 345/88, 348/671
• US Class Current: 345/89
• CPC Class Codes: G09G 3/2018 by time modulation using two or more time intervals
• CPC Class Codes: G09G 3/2051 with use of a spatial dither pattern
• CPC Class Codes: G09G 3/3611 Control of matrices with row and column drivers

Abstract

An LCD controller for use e.g. in a portable computer provides gray scale shading for both monochromatic and color displays using frame rate control modulation for intensity shading for each pixel. The gray scale shading process and circuit do not require any memory for storing phase tiling matrices or frame modulation pattern sequences; both of these instead are generated in real time using a linear matrix logic structure. Use of linear matrix operations also allows generation of various phase shifts of frame modulation pattern sequences to provide a better image on the display. In addition to providing programmable 4, 8, or 16 intensity levels, the present method and apparatus provide that vertically, horizontally or diagonally adjacent pixels on the display never have the same phase in the same frame, and in addition that the pixel display drivers are uniformly loaded.

Claims

1. A method for controlling pixel brightness levels for a digitally controlled display, comprising the steps of:

associating a duty cycle with each of a plurality of pixel brightness levels;

periodically generating a pattern by a matrix multiplication, the pattern defying a plurality of pixel phase shifts;

applying the pattern to assign one of the phase shifts to each pixel, for energizing the pixel at a particular duty cycle;

wherein the matrix multiplication includes;

matrix multiplying a matrix by itself p times;

where p indicates a phase shift amount; and

the step of applying includes;

for each phase shift, applying a pattern corresponding to the matrix multiplied by itself p times.

2. The method of claim 1, in which the step of periodically generating is programmable.

3. The method of claim 1, in which the generated pattern is repeated after n-1 phase shifts are generated, where n is a number of the pixel brightness levels.

4. The method of claim 1, wherein the matrix multiplication includes the step of:

multiplying a first matrix by a second matrix representing a set of programmable parameters to generate the pattern.

5. The method of claim 1, wherein the step of applying the pattern comprises the step of:

multiplying a first matrix representing the pattern by a second matrix representing a set of programmable parameters.

6. The method of claim 1, further comprising the steps of:

selecting a hashing matrix H to ensure that no two adjacent pixels have the same phase; and

applying the hashing matrix H to the assigned phase shifts.

7. A controller for a digitally controlled display having a plurality of pixels, each pixel operating at a plurality of brightness levels determined by energizing each pixel for an associated duty cycle, the controller comprising:

a clocked pattern generator, wherein the pattern generator periodically outputs a pattern signal defining one of p phases;

clocked phase selection multiplexer coupled to receive each of the pattern signals and periodically select a single output pattern;

wherein each pattern is applied to a signal representing a brightness level for a pixel, thereby to define a phase shift for the pixel; and

means for matrix multiplying a matrix by itself p times, where p indicates a phase shift amount for a pixel, and each applied pattern corresponds to the matrix multiplied by itself p times.

8. The controller of claim 7, further comprising a hashing element connected to a control terminal of the multiplexer, wherein the hashing element selects an output pattern such that no two adjacent pixels are in the same phase.

9. The controller of claim 7, wherein the pattern generator includes a plurality of exclusive-OR gates each having a plurality of input terminals, with each input terminal being connected to an output terminal of an AND gate, each AND gate having at least two input terminals respectively connected to a selector register and a source of a matrix value signal.

10. The controller of claim 7, wherein the controller generates and provides the selected patterns without use of pattern memory.

11. The controller of claim 7, further comprising:

means for matrix multiplying a matrix by itself p times, where p indicates a phase shift amount for a pixel, and each applied pattern corresponds to the matrix multiplied by itself p times.