Flash memory array and decoding architecture

• US 5,777,924 A
• Filed: 06/05/1997
• Issued: 07/07/1998
• Est. Priority Date: 06/05/1997
• Status: Expired due to Term

• Current Assignee: Secure Axcess LLC (Prism Technologies Group, Inc.)
• Original Assignee: Aplus Integrated Circuits Incorporated
• Inventors: Lee, Peter Wung, Tsao, Hsing-Ya, Hsu, Fu-Chang
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): PHAN, TRONG Q
• Application Number:
  US08/872,475
• Time in Patent Office: 397 Days
• Field of Search: 365/185.11, 365/185.22, 365/185.29, 365/185.33, 365/218
• US Class Current: 365/185.11
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 16/3404 Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
• CPC Class Codes: G11C 16/3409 Circuits or methods to recover overerased nonvolatile memory cells detected during erase verification, usually by means of a "soft" programming step
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification
• CPC Class Codes: G11C 8/14 Word line organisation; Word line lay-out
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A flash memory circuit having a word line decoder with even and odd word line latches and a source line decoder with a source line latch is disclosed. The word line decoders and source line decoder provide the capability of erasing the memory cells of two adjacent word lines in a flash memory simultaneously and verifying the memory cells word line by word line. By erasing two adjacent rows simultaneously, the embodiments of this invention eliminates over-erasure and source disturbance problems associated with conventional flash memory circuits. The decoding architecture provides flexible erase size that can be from a pair to a large number of multiple pairs of word lines. By dividing the memory cells of a word line into a number of segments, the decoding circuit further provides the capability of selecting the memory cells of a word line segment for erasing.

Claims

1. A flash memory array comprising:

a plurality of flash memory cells being arranged in a plurality of rows and a plurality of columns, each of said flash memory cells having a control gate, a drain a source;

a plurality of odd word lines each connecting the control gates of all the flash memory cells in a same odd row;

a plurality of even word lines each connecting the control gates of all the flash memory cells in a same even row;

a plurality of bit lines each connecting the drains of all the flash memory cells in a same column;

and a plurality of source lines each connecting the sources of all the flash memory cells in an odd row and an associated even row next to the odd row.

2. The flash memory array according to claim 1, further comprising at least a column of transistors each having a gate coupled to a word line of a row of memory cells for connecting the source line associated with the row to a source current draining line for shunting high cell current in a program operation, said associated source line being connected to a first ground and said source current draining line being connected to a second ground in a program operation.

3. The flash memory array according to claim 1, wherein each of said plurality of source lines is disconnected from the sources of the memory cells of an odd row and an associated even rows, said memory array is divided into a plurality of segments each comprising a number of columns, and each segment has a plurality of segmented source lines each being formed by wiring the sources of all the memory cells in an odd row and an associated even row next to the odd row within the segment together and then connected to the source line associated with the odd and even rows through at least one source segment control transistor having a gate coupled to a source segment control line of the segment.

4. The flash memory array according to claim 3, wherein said segmented source control line and said source segment control transistor are constructed with a first polysilicon layer, and said plurality of odd and even word lines and the control gates of said plurality of flash memory cells are formed by a second polysilicon layer.

5. A flash memory circuit having a plurality of flash memory banks each comprising:

a flash memory array including;

a plurality of flash memory cells being arranged in a plurality of rows and a plurality of columns, each of said flash memory cells having a control gate, a drain and a source;

a plurality of odd word lines each connecting the control gates of all the flash memory cells in a same odd row;

a plurality of even word lines each connecting the control gates of all the flash memory cells in a same even row;

a plurality of bit lines each connecting the drains of all the flash memory cells in a same column;

and a plurality of source lines each connecting the sources of all the flash memory cells in an odd row and an associated even row next to the odd row;

a bank decoder;

a source line voltage controlled by said bank decoder;

a source line decoder having;

a source control line;

a plurality of source primary address lines and source secondary address lines, each source primary address line having a corresponding source secondary address line; and

a plurality of source gating devices each being coupled to a source primary address line and a corresponding source secondary address line for connecting a source line to either said source line voltage or said source control line;

an odd word line voltage controlled by said bank decoder;

an even word line voltage controlled by said bank decoder;

and a word line decoder having;

a word control line;

a plurality of word primary address lines and word secondary address lines, each word primary address line having a corresponding word secondary address line;

and a plurality of word gating devices each being coupled to a word primary address line and a corresponding word secondary address line for connecting an odd word line to either said odd word line voltage or said word control line, or for connecting an even word line to either said even word line voltage or said word control line;

wherein an odd word gating device and an adjacent even word gating device being coupled to a same word primary address line and a same secondary address line for connecting an odd word line and an even word line respectively at the same time.

6. The flash memory circuit according to claim 5, further comprising:

a source line latch controlled by said bank decoder for providing said source line voltage;

an odd word line latch controlled by said bank decoder for providing said odd word line voltage;

and an even word line latch controlled by said bank decoder for providing said even word line voltage.

7. The flash memory circuit according to claim 6, each of said source gating devices further comprising first and second transistors having gates coupled to a source primary address line and a corresponding source secondary address line respectively for connecting a source line to either said source line latch or said source control line.

8. The flash memory circuit according to claim 6, each of said word gating devices further comprising:

a pair of n-channel and p-channel transistors having gates coupled to a word primary address line and a corresponding word secondary address line respectively for connecting an odd word line to said odd word line latch, or for connecting an even word line to said even word line latch;

and an n-channel transistor having a gate coupled to a word secondary address line for connecting an odd or even word line to said word control line;

wherein the word secondary address line coupled to said n-channel transistor is the same word secondary address line coupled to said pair of transistors and the word line connected by said n-channel transistor is the same word line connected by said pair of transistors.

9. The flash memory circuit according to claim 6, further comprising at least a column of transistors each having a gate coupled to a word line of a row of memory cells for connecting the source line associated with the row to a source current draining line for shunting high cell current in a program operation, said associated source line being connected to a first ground and said source current draining line being connected to a second ground in a program operation.

10. The flash memory circuit according to claim 6, each of said source gating devices further comprising:

first and second transistors having gates coupled to a source primary address line and a corresponding source secondary address line respectively for connecting a source line to either said source line latch or said source control line;

each of said word gating devices further comprising;

a pair of n-channel and p-channel transistors having gates coupled to a word primary address line and a corresponding word secondary address line respectively for connecting an odd word line to said odd word line latch, or for connecting an even word line to said even word line latch;

and an n-channel transistor having a gate coupled to a word secondary address line for connecting an odd or even word line to said word control line;

wherein the word secondary address line coupled to said n-channel transistor is the same word secondary address line coupled to said pair of transistors and the word line connected by said n-channel transistor is the same word line connected by said pair of transistors;

and said memory array further comprising;

at least a column of transistors each having a gate coupled to a word line of a row of memory cells for connecting the source line associated with the row to a source current draining line for shunting high cell current in a program operation, said associated source line being connected to a first ground and said source current draining line being connected to a second ground in a program operation.

11. The flash memory circuit according to claim 6, wherein each of said plurality of source lines is disconnected from the sources of the memory cells of an odd row and an associated even rows, said memory array is divided into a plurality of segments each comprising a number of columns, and each segment has a plurality of segmented source lines each being formed by wiring the sources of all the memory cells in an odd row and an associated even row next to the odd row within the segment together and then connected to the source line associated with the odd and even rows through at least one source segment control transistor having a gate coupled to a source segment control line of the segment.

12. The flash memory circuit according to claim 6, wherein said segmented source control line and said source segment control transistor are constructed with a first polysilicon layer, and said plurality of odd and even word lines and the control gates of said plurality of flash memory cells are formed by a second polysilicon layer.

13. A flash memory circuit having a plurality of flash memory banks each comprising:

a flash memory array including;

a plurality of flash memory cells being arranged in a plurality of rows and a plurality of columns, each of said flash memory cells having a control gate, a drain and a source;

a plurality of word lines each connecting the control gates of all the flash memory cells in a same row;

a plurality of bit lines each connecting the drains of all the flash memory cells in a same column;

and a plurality of source lines each connecting the sources of all the flash memory cells in an odd row and an associated even row next to the odd row;

a bank decoder;

a source line voltage controlled by said bank decoder;

a source line decoder having;

a source control line;

a plurality of source primary address lines and source secondary address lines, each source primary address line having a corresponding source secondary address line; and

a plurality of source gating devices each being coupled to a source primary address line and a corresponding source secondary address line for connecting a source line to either said source line voltage or said source control line;

a word control line controlled by said bank decoder;

a word line voltage controlled by said bank decoder;

and a word line decoder having;

a plurality of word primary address lines and word secondary address lines, each word primary address line having a corresponding word secondary address line;

and a plurality of word gating devices each being coupled to a word secondary address line and controlled by said word line voltage for connecting a word line to either a corresponding word primary address line or said word control line.

14. The flash memory circuit according to claim 13 further comprising:

a source line latch controlled by said bank decoder for providing said source line voltage;

a word control latch controlled by said bank decoder for providing said word control line;

and a word line latch controlled by said bank decoder for providing said word line voltage.

15. The flash memory circuit according to claim 14, each of said source gating devices further comprising first and second transistors having gates coupled to a source primary address line and a corresponding source secondary address line respectively for connecting a source line to either said source line latch or said source control line.

16. The flash memory circuit according to claim 14, each of said word gating devices further comprising:

a pair of p-channel and n-channel transistors having gates connected together and coupled to said word line latch for connecting a word line to a word primary address line or said word control latch;

and an n-channel transistor having a gate coupled to a word secondary address line for connecting the word line being connected to said pair of transistors to said word control latch;

wherein the word secondary address line coupled to said n-channel transistor is the corresponding word secondary address line of the word primary address line coupled to said pair of transistors.

17. The flash memory circuit according to claim 14, said memory array further comprising at least a column of transistors each having a gate coupled to a word line of a row of memory cells for connecting the source line associated with the row to a source current draining line for shunting high cell current in a program operation, said associated source line being connected to a first ground and said source current draining line being connected to a second ground in a program operation.

18. The flash memory circuit according to claim 14, each of said source gating devices further comprising:

first and second transistors having gates coupled to a source primary address line and a corresponding source secondary address line respectively for connecting a source line to either said source line latch or said source control line;

each of said word gating devices further comprising;

a pair of p-channel and n-channel transistors having gates connected together and coupled to said word line latch for connecting a word line to a word primary address line or said word control latch;

and an n-channel transistor having a gate coupled to a word secondary address line for connecting the word line being connected to said pair of transistors to said word control latch;

wherein the word secondary address line coupled to said n-channel transistor is the same word secondary address line coupled to said pair of transistors;

and said memory array further comprising;

at least a column of transistors each having a gate coupled to a word line of a row of memory cells for connecting the source line associated with the row to a source current draining line for shunting high cell current in a program operation, said associated source line being connected to a first ground and said source current draining line being connected to a second ground in a program operation.

19. The flash memory circuit according to claim 14, wherein each of said plurality of source lines is disconnected from the sources of the memory cells of an odd row and an associated even rows, said memory array is divided into a plurality of segments each comprising a number of columns, and each segment has a plurality of segmented source lines each being formed by wiring the sources of all the memory cells in an odd row and an associated even row next to the odd row within the segment together and then connected to the source line associated with the odd and even rows through at least one source segment control transistor having a gate coupled to a source segment control line of the segment.

20. The flash memory circuit according to claim 14, wherein said segmented source control line and said source segment control transistor are constructed with a first polysilicon layer, and said plurality of word lines and the control gates of said plurality of flash memory cells are formed by a second polysilicon layer.

21. A flash memory circuit having a plurality of flash memory banks each comprising:

a flash memory array including;

a plurality of flash memory cells being arranged in a plurality of rows and a plurality of columns, each of said flash memory cells having a control gate, a drain and a source;

a plurality of word lines each connecting the control gates of all the flash memory cells in a same row;

a plurality of bit lines each connecting the drains of all the flash memory cells in a same column;

and a plurality of source lines each connecting the sources of all the flash memory cells in an odd row and an associated even row next to the odd row;

a bank decoder;

a source line voltage controlled by said bank decoder;

a source line decoder having;

a source control line;

a plurality of source primary address lines and source secondary address lines, each source primary address line having a corresponding source secondary address line; and

a plurality of source gating devices each being coupled to a source primary address line and a corresponding source secondary address line for connecting a source line to either said source line voltage or said source control line;

a word control line controlled by said bank decoder;

a first word line voltage controlled by said bank decoder;

a second word line voltage controlled by said bank decoder; and

a word line decoder having;

a plurality of word primary address lines and word secondary address lines, each word primary address line having a corresponding word secondary address line;

and a plurality of word gating devices each being coupled to a word secondary address line and controlled by said first and second word line voltages for connecting a word line to either a corresponding word primary address line or said word control line.

22. The flash memory circuit according to claim 21 further comprising:

a source line latch controlled by said bank decoder for providing said source line voltage;

a word control latch controlled by said bank decoder for providing said word control line;

a first word line latch controlled by said bank decoder for providing said first word line voltage;

and a second word line latch controlled by said bank decoder for providing said second word line voltage.

23. The flash memory circuit according to claim 22, each of said source gating devices further comprising first and second transistors having gates coupled to a source primary address line and a corresponding source secondary address line respectively for connecting a source line to either said source line latch or said source control line.

24. The flash memory circuit according to claim 22, each of said word gating devices further comprising:

a pair of p-channel and n-channel transistors having gates coupled to said first and second word line latches respectively for connecting a word line to a word primary address line or to said word control latch;

and an n-channel transistor having a gate coupled to a word secondary address line for connecting the word line being connected to said pair of transistors to said word control latch;

wherein the word secondary address line coupled to said n-channel transistor is the corresponding word secondary address line of the word primary address line coupled to said pair of transistors.

25. The flash memory circuit according to claim 22, said memory array further comprising at least a column of transistors each having a gate coupled to a word line of a row of memory cells for connecting the source line associated with the row to a source current draining line for shunting high cell current in a program operation, said associated source line being connected to a first ground and said source current draining line being connected to a second ground in a program operation.

26. The flash memory circuit according to claim 22, each of said source gating devices further comprising:

first and second transistors having gates coupled to a source primary address line and a corresponding source secondary address line respectively for connecting a source line to either said source line latch or said source control line;

each of said word gating devices further comprising;

a plurality of word primary address lines and word secondary address lines, each word primary address line having a corresponding word secondary address line; and

a plurality of word gating devices each being coupled to a word secondary address line and controlled by said first and second word line voltages for connecting a word line to either a corresponding word primary address line or said word control line;

and said memory array further comprising;

at least a column of transistors each having a gate coupled to a word line of a row of memory cells for connecting the source line associated with the row to a source current draining line for shunting high cell current in a program operation, said associated source line being connected to a first ground and said source current draining line being connected to a second ground in a program operation.

27. The flash memory circuit according to claim 22, wherein each of said plurality of source lines is disconnected from the sources of the memory cells of an odd row and an associated even rows, said memory array is divided into a plurality of segments each comprising a number of columns, and each segment has a plurality of segmented source lines each being formed by wiring the sources of all the memory cells in an odd row and an associated even row next to the odd row within the segment together and then connected to the source line associated with the odd and even rows through at least one source segment control transistor having a gate coupled to a source segment control line of the segment.

28. The flash memory circuit according to claim 22, wherein said segmented source control line and said source segment control transistor are constructed with a first polysilicon layer, and said plurality of word lines and the control gates of said plurality of flash memory cells are formed by a second polysilicon layer.

29. A flash memory circuit having a plurality of flash memory banks each comprising:

a flash memory array including;

a plurality of flash memory cells being arranged in a plurality of rows and a plurality of columns, each of said flash memory cells having a control gate, a drain and a source;

a plurality of odd word lines each connecting the control gates of all the flash memory cells in a same odd row;

a plurality of even word lines each connecting the control gates of all the flash memory cells in a same even row;

a plurality of bit lines each connecting the drains of all the flash memory cells in a same column;

and a plurality of source lines each connecting the sources of all the flash memory cells in an odd row and an associated even row next to the odd row;

a bank decoder;

a source line voltage controlled by said bank decoder;

a source line decoder having;

a source control line;

a plurality of source primary address lines and source secondary address lines, each source primary address line having a corresponding source secondary address line; and

a plurality of source gating devices each being coupled to a source primary address line and a corresponding source secondary address line for connecting a source line to either said source line voltage or said source control line;

a word control line controlled by said bank decoder;

an odd word line voltage controlled by said bank decoder;

an even word line voltage controlled by said bank decoder;

and a word line decoder having;

a plurality of word primary address lines and word secondary address lines, each word primary address line having a corresponding word secondary address line;

and a plurality of word gating devices each being coupled to a word secondary address line and controlled by said odd word line voltage for connecting an odd word line to either a corresponding word primary address line or said word control line, or being coupled to a word secondary address line and controlled by said even word line voltage for connecting an even word line to either a corresponding word primary address line or said word control line;

wherein an odd word gating device and an adjacent even word gating device being coupled to a same word primary address line and a same secondary address line for connecting an odd word line and an even word line respectively at the same time.

30. The flash memory circuit according to claim 29, further comprising:

a source line latch controlled by said bank decoder for providing said source line voltage;

a word control latch controlled by said bank decoder for providing said word control line;

an odd word line latch controlled by said bank decoder for providing said odd word line voltage;

and an even word line latch controlled by said bank decoder for providing said even word line voltage.

31. The flash memory circuit according to claim 29, each of said source gating devices further comprising first and second transistors having gates coupled to a source primary address line and a corresponding source secondary address line respectively for connecting a source line to either said source line latch or said source control line.

32. The flash memory circuit according to claim 29, each of said word gating devices further comprising:

a pair of p-channel and n-channel transistors having gates connected together and coupled to said odd word line latch for connecting an odd word line to a word primary address line or to said word control latch, or having gates connected together and coupled to said even word line latch for connecting an even word line to a word primary address line or to said word control latch;

and an n-channel transistor having a gate coupled to a word secondary address line for connecting the word line being connected to said pair of transistors to said word control latch;

wherein the word secondary address line coupled to said n-channel transistor is the corresponding word secondary address line of the word primary address line coupled to said pair of transistors.

33. The flash memory circuit according to claim 29, said memory array further comprising at least a column of transistors each having a gate coupled to a word line of a row of memory cells for connecting the source line associated with the row to a source current draining line for shunting high cell current in a program operation, said associated source line being connected to a first ground and said source current draining line being connected to a second ground in a program operation.

34. The flash memory circuit according to claim 29, each of said source gating devices further comprising:

first and second transistors having gates coupled to a source primary address line and a corresponding source secondary address line respectively for connecting a source line to either said source line latch or said source control line;

each of said word gating devices further comprising;

a pair of p-channel and n-channel transistors having gates connected together and coupled to said odd word line latch for connecting an odd word line to a word primary address line or to said word control latch, or having gates connected together and coupled to said even word line latch for connecting an even word line to a word primary address line or to said word control latch;

and an n-channel transistor having a gate coupled to a word secondary address line for connecting the word line being connected to said pair of transistors to said word control latch;

wherein the word secondary address line coupled to said n-channel transistor is the corresponding word secondary address line of the word primary address line coupled to said pair of transistors;

and said memory array further comprising;

at least a column of transistors each having a gate coupled to a word line of a row of memory cells for connecting the source line associated with the row to a source current draining line for shunting high cell current in a program operation, said associated source line being connected to a first ground and said source current draining line being connected to a second ground in a program operation.

35. The flash memory circuit according to claim 29, wherein each of said plurality of source lines is disconnected from the sources of the memory cells of an odd row and an associated even rows, said memory array is divided into a plurality of segments each comprising a number of columns, and each segment has a plurality of segmented source lines each being formed by wiring the sources of all the memory cells in an odd row and an associated even row next to the odd row within the segment together and then connected to the source line associated with the odd and even rows through at least one source segment control transistor having a gate coupled to a source segment control line of the segment.

36. The flash memory circuit according to claim 29, wherein said segmented source control line and said source segment control transistor are constructed with a first polysilicon layer, and said plurality of odd and even word lines and the control gates of said plurality of flash memory cells are formed by a second polysilicon layer.

37. A method of simultaneously erasing the memory cells of two adjacent rows each having a word line and both sharing a source line in a selected memory bank of a flash memory circuit having a plurality of memory banks each including a bank decoder, a word line decoder and a source line decoder, comprising the steps of:

sending appropriate address signals to the word line decoder of the selected memory bank for selecting two adjacent word lines;

sending appropriate address signals to the source line decoder of the selected memory bank for selecting the source line shared by the selected adjacent word lines;

applying a first voltage to the selected adjacent word lines from said bank decoder of the selected memory bank;

applying a second voltage to the selected source line from said bank decoder of the selected memory bank;

and applying a third voltage to the word lines of other non-selected memory banks;

wherein said first and second voltages providing sufficient voltage difference for erasing the memory cells connected to the selected word lines.

38. The method of simultaneously erasing the memory cells of two adjacent rows according to claim 37, further including a method of erase-verifying the memory cells of the two erased rows one row at a time, said erase-verifying method comprising the steps of:

sending appropriate address signals to the word line decoder of the selected memory bank for selecting two erased adjacent word lines;

sending appropriate address signals to the source line decoder of the selected memory bank for selecting the source line shared by the selected adjacent word lines;

applying a third voltage to one of the selected adjacent word lines under verification from said bank decoder;

and applying a fourth voltage to the other word line of the selected adjacent word lines while a fifth voltage is applied to the word lines of other non-selected memory banks;

wherein said third voltage verifies if the memory cells connected to the word line under verification are erased properly, said fourth voltage provides a sufficiently low voltage for shutting off all the memory cells connected to the other word line of the selected adjacent word lines; and

said fifth voltage grounds all the word lines of other non-selected memory banks.

39. The method of simultaneously erasing the memory cells of two adjacent rows according to claim 38, wherein said bank decoder includes odd and even word line latches for providing voltages to odd and even word lines respectively, and a source line latch for providing a voltage to a source line.

40. A method of erase-verifying the memory cells of two erased adjacent rows each having a word line and both sharing a source line one row at a time in a selected memory bank of a flash memory circuit having a plurality of memory banks each including a bank decoder, a word line decoder and a source line decoder, comprising the steps of:

sending appropriate address signals to the word line decoder of the selected memory bank for selecting two erased adjacent word lines;

sending appropriate address signals to the source line decoder of the selected memory bank for selecting the source line shared by the selected adjacent word lines;

applying a first voltage to one of the selected adjacent word lines under verification from said bank decoder;

and applying a second voltage to the other word line of the selected adjacent word lines while a third voltage is applied to the word lines of other non-selected memory banks;

wherein said first voltage verifies if the memory cells connected to the word line under verification are erased properly, said second voltage provides a sufficiently low voltage for shutting off all the memory cells connected to the other word line of the selected adjacent word lines; and

said third voltage grounds all the word lines of other non-selected memory banks.

41. A method of memory operation for erasing and verifying one or more flash memory cells of a selected single word line in a flash memory circuit having a plurality of rows each having a word line, comprising the steps of:

a. locating a plurality of stressed flash memory cells including non-selected memory cells of said selected word line and all the memory cells of non-selected word lines that will suffer from memory data disturbance if said selected single word line is applied an erase bias condition;

b. reading data of said stressed flash memory cells and storing the data in a random access memory;

c. setting up said erase bias condition for erasing said selected single word line and bias conditions for other non-selected word lines;

d. applying an erase pulse to said selected word line for erasing one or more flash memory cells of said selected word line;

e. performing data verification for said one or more flash memory cells of said selected word line;

f. returning to step d. if said data verification of step e. fails and a pre-determined time limit is not exceeded, otherwise, continuing step g.

g. continuing step h. if said data verification of step e. succeeds, otherwise, going to step o.;

h. reading new data and executing data "1" verification for a first group of said stressed memory cells, said first group of stressed memory cells having data value "1" stored in said random access memory;

i. continuing step k. if said data "1" verification of step h. succeeds, otherwise executing step j.;

j. post-programming data "1" to the memory cells of said first group if said data "1" verification of step h. fails and a pre-determined time limit is not exceeded, and returning to step h., otherwise, going to step o.;

k. reading new data and executing data "0" verification for a second group of said stressed memory cells, said second group of stressed memory cells having data value "0" stored in said random access memory;

l. going to step n. if said data "0" verification of step k. succeeds, otherwise executing step m.;

m. post-programming data "0" to the memory cells of said second group if said data "0" verification of step k. fails and a pre-determined time limit is not exceeded, and returning to step k., otherwise, going to step o.;

n. exiting said memory operation successfully;

o. declaring said flash memory circuit defective and exiting said memory operation.