Method and device for error control of a macroblock-based video compression technique

• US 5,778,191 A
• Filed: 10/26/1995
• Issued: 07/07/1998
• Est. Priority Date: 10/26/1995
• Status: Expired due to Term

• Current Assignee: Google Technology Holdings LLC (Alphabet Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Brailean, James C., Levine, Stephen N., Banham, Mark R.
• Primary Examiner(s): Trammell, James P.
• Assistant Examiner(s): PEESO, THOMAS R
• Application Number:
  US08/548,385
• Time in Patent Office: 985 Days
• Field of Search: 364/514 R, 364/715.02, 348/19, 348/394, 348/415, 348/416, 348/420, 371/48, 395/114, 395/185.01, 395/200.77
• US Class Current: 709/247
• CPC Class Codes: H04N 19/00 Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
• CPC Class Codes: H04N 19/61 in combination with predictive coding
• CPC Class Codes: H04N 19/70 characterised by syntax aspects related to video coding, e.g. related to compression standards
• CPC Class Codes: H04N 19/89 involving methods or arrangements for detection of transmission errors at the decoder

Abstract

The present invention provides a method (200) and device (300) for error control of a video compressed sequence in which error protection for both random and burst channel errors is provided. The error control syntax (100) applies a fixed length packet synchronization system to variable length coded compressed video data, which provides the capability to limit error propagation within the decoded video bit stream. The fixed length packet control information provides information to decode compressed video data in both forward and reverse directions to allow for the recovery of correctly decoded video data within a decoded frame after long bursts of channel errors while reducing the overhead for error control. The error control method also provides video error detection which may be used for error concealment.

Claims

1. A method of error control of a macroblock-based video codec, wherein macroblocks are encoded using entropy coding, comprising:

A) utilizing, in a decoder, control information and a plurality of picture headers in fixed positions relative to a beginning of a frame wherein the control information provides decoding information for decoding at least a forward sequence of macroblocks;

B) detecting errors in the frame and limiting propagation of errors in the frame utilizing the control information and the plurality of picture headers,

wherein the control information defines a boundary of individual packets and includes;

C) an absolute count of a next/previous macroblock within the frame;

D) a relative address of a start of a next macroblock in a next packet; and

E) absolute values for predetermined differentially encoded information,

where the relative address is quantized to bytes, and where a quantization remainder determines a number of bits available for an error detection code.

2. The method of claim 1 wherein the predetermined differentially encoded information includes at least one of:

A) a quantization parameter of an immediately previous macroblock; and

B) a motion vector value of the immediately previous macroblock.

3. The method of claim 1 wherein detecting an error in the frame includes detecting an error in the packet wherein at least one of:

A) detecting loss of entropy coding synchronization;

B) determining whether the absolute count is decreasing;

C) detecting an incorrect error detection code; and

D) determining whether invalid coding parameters are present.

4. The method of claim 1 wherein at least one of the picture headers is utilized to determine a start of the frame.

5. The method of claim 1 wherein the method is a process whose steps are embodied in least one of:

A) an application specific integrated circuit;

B) a field programmable gate array; and

C) a microprocessor; and

D) a computer-readable memory;

arranged and configured to determine the first modified received signal having minimized distortion and interference in accordance with the scheme of claim 1.

6. The method of claim 1 wherein the control information defines a boundary of individual packets and includes:

A) an absolute count of a next/previous macroblock within the frame;

B) a resynchronization start code inserted at the first bit of a next macroblock within the frame; and

C) absolute values for predetermined differentially encoded information.

7. The method of claim 6 wherein the predetermined differentially encoded information includes at least one of:

A) a quantization parameter of an immediately previous macroblock; and

B) a motion vector value of the immediately previous macroblock.

8. The method of claim 6 wherein detecting an error in the frame includes detecting an error in the packet wherein at least one of:

A) detecting loss of entropy coding synchronization;

B) determining whether the absolute count is decreasing;

C) detecting an incorrect error detection code; and

D) determining whether invalid coding parameters are present.

9. The method of claim 6 further including that encoding of the macroblocks includes outputting the macroblocks in a forward bit order for a predetermined number of macroblocks and in a bit-reversed bit order for a second predetermined number of macroblocks and wherein a control information is used to decode both forward and reverse bit encoded macroblocks.

10. The method of claim 9 wherein an error detection code is inserted between the forward and bit-reversed maroblocks.

13. The method of claim 2 wherein the relative address is quantized to bytes, and where a quantization remainder determines a numbers of bits available for an error detection code.

15. The method of claim 11 wherein the method is a process whose steps are embodied in least one of:

A) an application specific integrated circuit;

B) a field programmable gate array; and

C) a microprocessor; and

D) a computer-readable memory;

arranged and configured to determine the first modified received signal having minimized distortion and interference in accordance with the scheme of claim 1.

11. A method of error control of a macroblock-based video codec, wherein macroblocks are encoded using entropy coding, comprising:

A) utilizing, in a decoder, control information and a plurality of picture headers in fixed positions relative to a beginning of a frame wherein the control information provides decoding information for decoding at least a forward sequence of macroblocks;

B) detecting errors in the frame and limiting propagation of errors in the frame utilizing the control information and the plurality of picture headers,

wherein the control information defines a boundary of individual packets and includes;

C) an absolute count of a next/previous macroblock within the frame;

D) a relative address of a start of a next macroblock in a next packet; and

E) absolute values for predetermined differentially encoded information,

further including that encoding of the macroblocks includes outputting the macroblocks in a forward bit order for a predetermined number of macroblocks and in a bit-reversed bit order for a second predetermined number of macroblocks and wherein a control information is used to decode both forward and reverse bit encoded macroblocks.

12. The method of claim 11 wherein an error detection code is inserted between the forward and bit-reversed marcroblocks.

14. The method of claim 11 wherein at least one of the picture headers is utilized to determine a start of the frame.

16. A device for error control and concealment of a macroblock-based video codec, wherein macroblocks are encoded using entropy coding, wherein the device is directed by a computer program that is embodied in at least one of:

A) a memory;

B) an application specific integrated circuit;

C) digital signal processor; and

D) a field programmable gate array, and the computer program includes steps of;

E) utilizing control information and a plurality of picture headers in fixed positions relative to a beginning of a frame wherein the control information provides decoding information for decoding at least a forward sequence of macroblocks;

F) detecting errors in the frame and limiting propagation of errors in the frame utilizing the control information and the plurality of picture headers,

wherein the control information computed by a bit packer controller defines a boundary of individual packets and includes;

G) an absolute count of a next/previous macroblock within the frame;

H) a relative address of a start of a next macroblock in a next packet; and

I) absolute values for predetermined differentially encoded information,

where the relative address is quantized to bytes, and where a quantization remainder determines a number of bits available for an error detection code.

17. The device of claim 16 wherein the predetermined differentially encoded information includes at least one of:

A) a quantization parameter of an immediately previous macroblock; and

B) a motion vector value of the immediately previous macroblock.

18. The device of claim 16 wherein the an error detection unit performs detecting of an error in a packet wherein at least one of:

A) detecting loss of entropy coding synchronization;

B) determining whether the absolute count is decreasing;

C) detecting an incorrect error detection code; and

D) determining whether invalid coding parameters are present.

19. The device of claim 16 further including two block-based bit reversers utilized such that encoding of the macroblocks includes outputting the macroblocks in a forward bit order for a predetermined number of macroblocks and in a bit-reversed bit order for a second predetermined number of macroblocks and wherein a control information is used to decode both forward and reverse bit encoded macroblocks.

20. The device of claim 19 wherein an error detection code is inserted between the forward and bit-reversed maroblocks.

21. The device of claim 20 wherein the relative address is quantized to bytes, and where a quantization remainder determines a number of bits available for an error dection code.

22. The device of claim 16 wherein at least one of the picture headers is utilized to determine a start of the frame.

23. A device for error control and concealment for packets in a compressed bitstream in a macroblock-based video codec, wherein macroblocks are encoded using entropy coding, and a fixed length packet synchronization system is applied to variable length coded compressed video data, to limit error propagation within a decoded video bitstream, wherein the device comprises at least one of an encoder and a decoder,

wherein the encoder comprises:

A) a bit packet controller, coupled to receive a compressed bitstream, for computing error control information by generating a plurality of predetermined control words, wherein packet control information is placed at a beginning of each packet;

B) a block-based bit reverser, coupled to receive the compressed bitstream and to the bit packet controller, for reversing a macroblock bit order for macroblocks that are designated as backwards encoded macroblocks; and

C) a multiplexer, coupled to the bit packet controller, the compressed bitstream and to the block-reversed bit reverser, for multiplexing the error control information and the compressed bitstream with the output of the block-based bit reverser according to a predetermined scheme;

and in the decoder comprises;

D) a demultiplexer, coupled to receive a multiplexed bitstream and to a control unit, for removing bits indicated by the control unit in accordance with a predetermined scheme and sending the bits to a second block-based bit reversal unit, a forward block decoder, and an error detector;

E) the second block-based bit reversal unit, coupled to the demultiplexer, for reversing a macroblock bit order for macroblocks in accordance with the predetermined scheme to provide an output; and

F) a backward block decoder, coupled to the second block-based bit reversal unit, for decoding the output of the second block-based bit reversal unit;

G) a forward block decoder, coupled to the demultiplexer, for decoding the bits from the demultiplexer;

H) an error detector, coupled to the demultiplexer, the backward block decoder, and to the forward block decoder, for utilizing control information and the decoded bitstreams to signal a presence of specific errors.

24. The device of claim 23 further including an error report unit, coupled to the error detector, for outputting an error report, for utilization in error concealment, wherein the error report including at least one of:

loss of entropy coding synchronization, errors in an absolute count due to a decreasing count, cyclic redundancy count errors, other coding parameters detected that have been preselected to indicate invalidity, and variable length decoder errors.

25. The device of claim 23, wherein the bit packet controller generates at least the following control words:

picture headers;

absolute count, AC, of next macroblock in the bistream;

relative address, AD, of the next macroblock in the bitstream in bytes;

absolute quantization parameter value, QP, of the last macroblock in a present packet of bits, absolute motion vector, MV, associated with the last macroblock in the present packet of bits; and

a check word, CRC, providing error detection capabilities for the present packet of bits.