Method and apparatus for dynamic allocation of multiple buffers in a processor
First Claim
1. A pipelined processor comprising:
- a reorder buffer containing result information generated by speculative instructions;
a reservation station coupled to said reorder buffer, said reservation station containing information associated with instructions pending execution; and
an allocator coupled to said reorder buffer and said reservation station, said allocator allocating entries of said reorder buffer and said reservation station during an allocation pipestage of said pipelined processor, said allocation pipestage following a decode pipestage of said pipelined processor and preceding a dispatch pipestage of said pipelined processor, said allocator locating entries of said reservation station for each pending instruction except for one or more register exchange instructions.
1 Assignment
0 Petitions
Accused Products
Abstract
A method and apparatus for dynamically allocating entries of microprocessor resources to particular instructions in an efficient manner to efficiently utilize buffer size and resources. The pipelined and superscalar microprocessor is capable of speculatively executing instructions and also out-of-order processing. Resources within the microprocessor include a store buffer, a load buffer, a reorder buffer and a reservation station. The reorder buffer contains a larger set of physical registers and also contains information related to speculative instructions and the reservation station comprises information related to instructions pending execution. The load buffer is only allocated to load instructions and is valid for an instruction from allocation pipestage to instruction retirement. The store buffer is only allocated to store instructions and is valid for an instruction from allocation to store performance. The reservation station is allocated to most instructions and is valid for an instruction from allocation to instruction dispatch. The reorder buffer is allocated to all instructions and is valid for a given instruction from allocation to retirement. The load buffer, store buffer, and reorder buffer are sequentially allocated while the reservation station is not. Resource allocation is performed dynamically (as needed by the operation) rather than as a full set of resources attached to each operation. Using the above allocation scheme, efficient usage of the microprocessor resources is accomplished.
-
Citations
22 Claims
-
1. A pipelined processor comprising:
-
a reorder buffer containing result information generated by speculative instructions; a reservation station coupled to said reorder buffer, said reservation station containing information associated with instructions pending execution; and an allocator coupled to said reorder buffer and said reservation station, said allocator allocating entries of said reorder buffer and said reservation station during an allocation pipestage of said pipelined processor, said allocation pipestage following a decode pipestage of said pipelined processor and preceding a dispatch pipestage of said pipelined processor, said allocator locating entries of said reservation station for each pending instruction except for one or more register exchange instructions. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
-
-
9. A computer system comprising:
-
a bus for communicating information; a memory storage unit coupled to said bus for storing information; a first processor coupled to said bus; and a second processor coupled to the bus, the second processor being a pipelined processor comprising; a reorder buffer containing result information generated by speculative instructions; a reservation station coupled to said reorder buffer, said reservation station containing information associated with instructions pending execution; and an allocator coupled to said reorder buffer and said reservation station, said allocator allocating entries of said reorder buffer and said reservation station during an allocation pipestage of said pipelined processor, said allocation pipestage following a decode pipestage of said pipelined processor and preceding a dispatch pipestage of said pipelined processor, said allocator allocating entries of said reservation station for each pending instruction except for one or more register exchange instructions. - View Dependent Claims (10, 11, 12, 13, 14)
-
-
15. In a pipeline processor having a pipeline comprising allocation, dispatch and retirement pipestages, a method of dynamically allocating resources in said processor, said method comprising the steps of:
-
(a) allocating entries of a first buffer to instructions during said allocation pipestage and until said retirement pipestage for said instructions, wherein said first buffer contains information associated with speculative instructions; (b) allocating entries of a reservation station to instructions during said allocation pipestage and until said dispatch pipestage, wherein said reservation station contains information associated with instructions pending execution; and wherein said step (b) of allocating entries of a reservation station is performed for each instruction processed by said processor except for one or more register exchange instructions. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22)
-
Specification