Floating gate memory device and method for terminating a program load cycle upon detecting a predetermined address/data pattern
First Claim
1. An integrated circuit memory, comprising:
- an array of storage elements;
input/output circuitry, having inputs to receive addresses and data and coupled to the array, to read and store data segments in the array in response to the addresses and the data on the inputs; and
command logic, coupled to the input/output circuitry, which executes a process to store a block of data in response to a sequence of addresses and data segments received at the input/output circuitry, including logic to detect a last segment of the block of data in response to a pattern including at least one of the addresses and the data received at the input/output circuitry.
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Accused Products
Abstract
A floating gate memory with a protocol which terminates a program load cycle upon detecting a predetermined address and/or data pattern, providing positive indication of the end of the load cycle, and eliminating the requirement for a long pulse in a controlled signal. Command logic executes a process to store a block of data in response to a sequence of addresses and data segments received at the input/output circuitry, and detects the last segment in a block of data in response to a pattern including at least one of the addresses and data segments received at the input/output circuitry. One pattern includes consecutive matching addresses. Pattern match logic included in the command logic is coupled to the input/output circuitry and stores addresses in the sequence and compares them with a next address to indicate a matching address. Alternatively, the pattern includes both matching addresses and data segments with corresponding comparator circuitry. Alternatively, the pattern comprises a command address which is outside the address field of the memory array. The command address may include all or only a high order segment of the actual data address. The floating gate memory includes a state machine which automatically programs and verifies programming of the block of data after the last segment of the block is detected, and may comprise a flash memory or electrically erasable programmable read only memory (EEPROM).
143 Citations
40 Claims
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1. An integrated circuit memory, comprising:
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an array of storage elements; input/output circuitry, having inputs to receive addresses and data and coupled to the array, to read and store data segments in the array in response to the addresses and the data on the inputs; and command logic, coupled to the input/output circuitry, which executes a process to store a block of data in response to a sequence of addresses and data segments received at the input/output circuitry, including logic to detect a last segment of the block of data in response to a pattern including at least one of the addresses and the data received at the input/output circuitry. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A floating gate memory circuit on a semiconductor substrate comprising:
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a memory array including at least M rows and N columns of floating gate cells; M word lines, each coupled to the floating gate cells in one of the M rows of floating gate cells; a plurality of bit lines, each coupled to the floating gate cells in at least one of the N columns of floating gate cells; input/output circuitry, having inputs to receive addresses and data; command logic, coupled to the input/output circuitry, which executes a process to store a block of data in response to a sequence of addresses and data segments received at the input/output circuitry, including logic to detect a last segment of the block of data in response to a pattern including at least one of the addresses and data received at the input/output circuitry; a page buffer, coupled to the input/output circuitry to store the block of data and supply the block of data to the N columns of floating gate cells; write control circuitry, coupled to the command logic, the page buffer and the M word lines, which after detection of the last segment in the block, supplies programming voltages to a selected word line for programming input data to a row of floating gate cells accessed by the selected word line in response to the block of data stored in the page buffer; and program verify circuitry, coupled to the page buffer, which verifies that floating gate cells are programmed with the block of data in the page buffer. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30)
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31. A method for storing a block of data consisting of less than or equal to a page in a floating gate memory device, comprising:
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supplying a command which indicates an automatic program operation to the memory device; after supplying the command, supplying a stream of addresses and segments of data, and storing the supplied segments in a page buffer; monitoring the supplied stream of addresses and segments of data to detect a pattern in the supplied stream which signals an end of the block of data; and after detection of the pattern, executing a program operation to store the block of data from the page buffer into the floating gate memory device. - View Dependent Claims (32, 33, 34, 35, 36, 37, 38, 39, 40)
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Specification