Method and apparatus for reset-sensitive and controlled register write accesses in a data processing system with user and test modes

• US 5,778,444 A
• Filed: 05/06/1996
• Issued: 07/07/1998
• Est. Priority Date: 05/06/1996
• Status: Expired due to Fees

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Drake, Philip B., Leiser, Rebecca A., Langan, John A.
• Primary Examiner(s): Swann, Tod R.
• Assistant Examiner(s): LANGJAHR, DAVID
• Application Number:
  US08/643,647
• Time in Patent Office: 792 Days
• Field of Search: 395/500, 395/535, 395/657, 395/490, 395/412, 711/163
• US Class Current: 711/163
• CPC Class Codes: G06F 11/3656 using a specific debug interface

Abstract

A method for accessing a control register in a data processing system which ignores a first write to sensitive control bits when in a first mode, but allows subsequent writes to the sensitive control bits. When operating in a user mode, the method allows a first write to the sensitive control bits, but does not allow any subsequent writes. When a write access is made to the sensitive control bits during test mode only non-initial writes are effective. When a write access is made to the sensitive control bits during user mode only an initial write is effective. The method is effective in a data processing system having a control register write access scheme.

Claims

1. A method for operating a data processor, said method comprising the steps of:

performing a first write access to a first control bit, the first write access being an initial write access after a reset of the data processor, wherein the first control bit is for configuring at least one parameter of the data processor;

causing the first write access to the first control bit to have no effect on the first control bit;

performing a second write access to the first control bit, wherein the second write access is subsequent to the first write access;

causing the second write access to the first control bit to affect the first control bit;

performing a third write access to the first control bit, wherein the third write access is subsequent to the second write access; and

causing the third write access to the first control bit to affect the first control bit.

2. A method as in claim 1, further comprising the steps of:

performing a first write access to a second control bit;

causing the first write access to the second control bit to have no effect on the second control bit;

performing a second write access to the second control bit; and

causing the second write access to the second control bit to affect the second control bit.

3. A method as in claim 2, wherein the first control bit and the second control bit are part of a control register.

4. A method as in claim 1, where said data processor is in a first operating mode.

5. A method as in claim 4, wherein the first operating mode is used for emulation.

6. A method as in claim 4, wherein the step of performing the first write access to the first control bit further comprises:

if the data processor is in a second operating mode causing the first write access to the first control bit to affect the first control bit.

7. A method as in claim 6, wherein the step of performing the second write access to the first control bit further comprises:

if the data processor is in the second operating mode causing the second write access to the first control bit to have no effect on the first control bit.

8. A method as in claim 6, wherein the second operating mode is a user mode.

9. A method as in claim 4, wherein the first operating mode is used for test.

10. An integrated circuit, said integrated circuit comprising:

a register; and

control circuitry coupled to the register for determining if a present write access to the register is a first write access after reset;

wherein if the present write access to the register is the first write access to the register after reset, said control circuitry will cause the present write access to the register to have no effect on the register; and

wherein if the present write access to the register is not the first write access to the register after reset, said control circuitry will cause the present write access to the register to affect the register by writing to the register.

11. A integrated circuit as in claim 10, wherein said integrated circuit is in a first operating mode.

12. An integrated circuit as in claim 11, said integrated circuit has a second operating mode,

wherein if the present write access to the register is the first write access to the register after reset, said control circuitry will cause the present write access to the register to affect the register by writing to the register;

and

wherein if the present write access to the register is not the first write access to the register after reset, said control circuitry will cause the present write access to the register to have no effect on the register.

13. An integrated circuit as in claim 12, further comprising:

a memory storage unit storing an application program compatible with the first operating mode and the second operating mode.

14. An integrated circuit as in claim 13, wherein the first operating mode is used for emulation.

15. An integrated circuit as in claim 10, wherein the register comprises control bits.

16. An integrated circuit as in claim 10, wherein the register comprises control bits and status bits.

17. A method for operating a data processor, said method comprising the steps of:

resetting the data processor, wherein a control register for configuring the data processor is enabled;

performing a first write access to a first control bit in the control register, the first write access being an initial write access after reset while the control register is enabled;

causing the first write access to the first control bit to have no effect on the first control bit;

performing a second write access to the first control bit, wherein the second write access is subsequent to the first write access while the control register is enabled; and

causing the second write access to the first control bit to affect the first control bit.

18. The method of claim 17 further comprising the steps of:

performing a first write access to a second control bit;

causing the first write access to the second control bit to have no effect on the second control bit;

performing a second write access to the second control bit; and

causing the second write access to the second control bit to affect the second control bit.

19. The method of claim 17 further comprising the step of placing the data processor in a first operating mode which causes the first write access to the first control bit to have no effect on the first control bit.