Methods of forming integrated circuit memory devices having improved storage electrode contact regions therein

• US 5,780,336 A
• Filed: 12/30/1996
• Issued: 07/14/1998
• Est. Priority Date: 08/21/1996
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Son, Jin-young
• Primary Examiner(s): TSAI, H JEY
• Application Number:
  US08/773,195
• Time in Patent Office: 561 Days
• Field of Search: 437/919, 437/52, 438/238-239, 438/250-256, 438/381, 438/393-399
• US Class Current: 438/251
• CPC Class Codes: H10B 12/01 Manufacture or treatment

Abstract

Methods of forming integrated circuit memory devices, such as DRAM memory cells, include the steps of performing a relatively low dose plug implantation step preferably prior to and after formation of a buried contact hole to expose a storage electrode contact region in a semiconductor substrate. By performing a plug implantation step at a low level prior to formation of a buried contact hole (and after), a memory cell having improved refresh characteristics can be achieved. In particular, the performance of the plug implantation step prior to and after formation of the buried contact hole compensates for substrate damage caused during formation of field oxide isolation regions adjacent the memory cell and during formation of the buried contact hole when the storage electrode contact region is exposed to an etchant.

Claims

1. A method of forming an integrated circuit memory device, comprising the steps of:

forming a field oxide isolation region at a face of semiconductor substrate;

forming an insulated electrode of a memory cell on the face, adjacent the field oxide isolation region;

implanting dopants of first conductivity type into the face using the insulated electrode as an implant mask to define a storage electrode contact region of first conductivity type between the insulated electrode and the field oxide isolation region;

then

forming sidewall spacers on first and second opposing edges of the insulated electrode;

implanting dopants of first conductivity type into the storage electrode contact region at a dose level in a range between about 1×

10¹² cm^-2 and 3×

10¹³ cm^-2 and at an energy in a range between about 10 KeV and 300 KeV, using the insulated electrode and sidewall spacers as an implant mask; and

forming an electrode of a storage capacitor coupled to the storage electrode contact region, on the substrate.

2. The method of claim 1, further comprising the steps of:

forming a first electrically insulating layer on the field oxide isolation region, sidewall spacers and insulated electrode;

patterning a bit line on the first electrically insulating layer;

forming a second electrically insulating layer on the first electrically insulating layer and the bit line;

forming a contact hole in the first and second electrically insulating layers to expose the storage electrode contact region; and

implanting dopants of first conductivity type through the contact hole and into the storage electrode contact region.

3. The method of claim 2, wherein said step of forming an electrode of a storage capacitor comprises patterning a layer of metallization in the contact hole.

4. The method of claim 2, wherein said step of implanting dopants of first conductivity type through the contact hole comprises implanting dopants of first conductivity type at a dose level in a range between about 1×

10¹² cm^-2 and 3×

10¹³ cm^-2 and at an energy in a range between about 10 KeV and 300 KeV.

5. The method of claim 3, wherein said step of implanting dopants of first conductivity type through the contact hole comprises implanting dopants of first conductivity type at a dose level in a range between about 1×

10¹² cm^-2 and 3×

10¹³ cm^-2 and at an energy in a range between about 10 KeV and 300 KeV.

6. A method of forming an integrated circuit memory device, comprising the steps of:

forming a semiconductor substrate containing a memory cell array region of first conductivity type therein extending to a face thereof at a first location and a peripheral circuit region of first conductivity type therein extending to the face at a second location spaced from the first location;

forming an insulated electrode of a memory cell on the memory cell array region and an insulated electrode of a field effect transistor on the peripheral circuit region;

forming sidewall spacers on sidewalls of the insulated electrode of the memory cell and on sidewalls of the insulated electrode of the field effect transistor;

implanting dopants of second conductivity type in the memory cell array region at a first dose level using the insulated electrode of the memory cell and respective sidewall spacers as an implant mask to define a storage electrode contact region;

implanting dopants of second conductivity type in the peripheral circuit region at a second dose level, greater than the first dose level, using the insulated electrode of the field effect transistor and respective sidewall spacers as an implant mask to define source and drain regions;

forming a first electrically insulating layer on the insulated electrode of the memory cell;

forming a contact hole in the first electrically insulating layer to expose the storage electrode contact region;

implanting dopants of second conductivity type through the contact hole and into the storage electrode contact region;

forming an electrode of a storage capacitor coupled to the storage electrode contact region, on the first electrically insulating layer; and

wherein said step of implanting dopants of second conductivity type through the contact hole comprises implanting phosphorus at a dose level in a range between about 1×

10¹² cm^-2 and 3×

10¹³ cm^-2 and at an energy in a range between about 10 KeV and 300 KeV.

7. The method of claim 6, wherein said step of implanting dopants of second conductivity type to define a storage electrode contact region comprises implanting dopants of second conductivity type at a dose level in a range between about 1×

10¹² cm^-2 and 3×

10¹³ cm^-2 and at an energy in a range between about 10 KeV and 300 KeV.

8. The method of claim 7, wherein said step of forming a contact hole is preceded by the steps of:

patterning a bit line of the first electrically insulating layer; and

forming a second electrically insulating layer on the first electrically insulating layer and the bit line.

9. The method of claim 8, wherein said step of implanting dopants of second conductivity type through the contact hole comprises implanting phosphorus at a dose level in a range between about 1×

10¹² cm^-2 and 3×

10¹³ cm^-2 and at an energy in a range between about 10 KeV and 300 KeV.

10. The method of claim 7, wherein said step of implanting dopants of second conductivity type through the contact hole comprises implanting phosphorus at a dose level in a range between about 1×

10¹² cm^-2 and 3×

10¹³ cm^-2 and at an energy in a range between about 10 KeV and 300 KeV.