Method of forming trench transistor and isolation trench

• US 5,780,340 A
• Filed: 10/30/1996
• Issued: 07/14/1998
• Est. Priority Date: 10/30/1996
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Cheek, Jon D., Kadosh, Daniel, Gardner, Mark I.
• Primary Examiner(s): DANG, TRUNG Q
• Application Number:
  US08/739,566
• Time in Patent Office: 622 Days
• Field of Search: 438/296, 438/257, 438/259, 438/430, 438/424, 438/227
• US Class Current: 438/259
• CPC Class Codes: H01L 21/76 Making of isolation regions between components
• CPC Class Codes: H01L 29/66583 with initial gate mask or masking layer complementary to the prospective gate location, e.g. with dummy source and drain contacts
• CPC Class Codes: H01L 29/66613 with a gate recessing step, e.g. using local oxidation making recessed gate LDMOS transistors H01L29/66704
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar

Abstract

An IGFET with a gate electrode in a transistor trench adjacent to an isolation trench is disclosed. The trenches are formed in a semiconductor substrate. A gate insulator is on a bottom surface of the transistor trench, insulative spacers are adjacent to opposing sidewalls of the transistor trench, and the gate electrode is on the gate insulator and spacers and is electrically isolated from the substrate. Substantially all of the gate electrode is within the transistor trench. A source and drain in the substrate are beneath and adjacent to the bottom surface of the transistor trench. The isolation trench is filled with an insulator and provides device isolation for the IGFET. Advantageously, the trenches are formed simultaneously using a single etch step.

Claims

1. A method of forming an IGFET and an isolation trench, comprising the steps of:

simultaneously forming a transistor trench and an isolation trench in a substrate, wherein

the transistor trench includes first and second opposing sidewalls and a first bottom surface, and the isolation trench includes third and fourth opposing sidewalls and a second bottom surface;

forming first and second spacers adjacent to the first and second sidewalls, respectively;

forming a gate insulator on the first bottom surface;

forming a gate electrode on the gate insulator and the spacers; and

forming a source and a drain in the substrate and adjacent to the first bottom surface.

2. The method of claim 1, including forming third and fourth spacers adjacent to the third and fourth sidewalls, respectively, simultaneously with forming the first and second spacers.

3. The method of claim 2, wherein forming the first, second, third and fourth spacers includes depositing an insulative material over the substrate and into the trenches and then applying an anisotropic etch.

4. The method of claim 1, wherein forming the gate electrode includes depositing a polysilicon layer over the substrate and into the trenches, and then polishing the polysilicon layer until polysilicon regions in the trenches do not overlap a top surface of the substrate.

5. The method of claim 1, including filling the isolation trench with an insulator.

6. The method of claim 5, wherein filling the isolation trench with an insulator includes forming third and fourth spacers adjacent to the third and fourth sidewalls, respectively, and then depositing an insulative layer over the substrate and into the isolation trench.

7. The method of claim 6, wherein the insulative layer is undoped polysilicon.

8. The method of claim 6, wherein the insulative layer is silicon dioxide.

9. The method of claim 1, wherein the first and second bottom surfaces have essentially identical depths beneath a top surface of the substrate.

10. The method of claim 1, wherein a length between the first and second sidewalls is essentially identical to a length between the third and fourth sidewalls.

11. A method of forming an IGFET and an isolation trench filled with an insulator for providing device isolation for the IGFET, comprising the steps of:

simultaneously etching a transistor trench and an isolation trench in a semiconductor substrate, wherein the transistor trench includes first and second opposing sidewalls and a first bottom surface, the isolation trench includes third and fourth opposing sidewalls and a second bottom surface, and the first and second bottom surfaces have essentially identical depths beneath a top surface of the substrate;

simultaneously forming first and second spacers adjacent to the first and second sidewalls, respectively, and third and fourth spacers adjacent to the third and fourth sidewalls, respectively;

simultaneously forming a gate insulator on a central portion of the first bottom surface between the first and second spacers and an insulative region on a central portion of the second bottom surface between the third and fourth spacers;

depositing a gate electrode material over the substrate, on the first, second, third and fourth spacers, on the gate insulator and insulative region, and into the trenches;

polishing the gate electrode material such that a first portion of the gate electrode material in the transistor trench provides a gate electrode and a second portion of gate electrode material is in the isolation trench; and

forming a source and a drain in the substrate, wherein the source is adjacent to the first bottom surface and the first sidewall and the top surface, and the drain is adjacent to the first bottom surface and the second sidewall and the top surface.

12. The method of claim 11, including:

forming a masking layer over the substrate that covers the transistor trench and exposes the isolation trench;

removing the second portion of the gate electrode material without removing the gate electrode;

stripping the masking material; and

then

depositing a second insulator into the isolation trench.

13. The method of claim 12, including polishing the second insulator until a top surface of the second insulator is planar and aligned with a top surface of the gate electrode.

14. The method of claim 12, including polishing the second insulator until a top surface of the second insulator is planar and above a top surface of the gate electrode, forming contact windows in the second insulator above the source, drain, and gate electrode, and depositing interconnect metallization in the contact windows.

15. The method of claim 11, including providing all doping for the source and the drain before simultaneously etching the trenches.

16. The method of claim 11, including providing doping for the source and the drain both before and after simultaneously etching the trenches.

17. The method of claim 11, including providing all doping for the source and the drain after simultaneously etching the trenches.

18. The method of claim 11, wherein a lightly doped region of the source spaced from the top surface provides a first channel junction beneath and adjacent to the first bottom surface, a lightly doped region of the drain spaced from the top surface provides a second channel junction beneath and adjacent to the first bottom surface, a heavily doped region of the source spaced from the first channel junction is adjacent to the first sidewall and the top surface, and a heavily doped region of the drain spaced from the second channel junction is adjacent to the second sidewall and the top surface.

19. The method of claim 11, wherein the IGFET is an N-channel MOSFET.

20. The method of claim 11, wherein the IGFET is a P-channel MOSFET.

21. A method of forming an IGFET adjacent to an isolation trench filled with oxide for providing device isolation for the IGFET, comprising the steps of:

providing a semiconductor substrate with a planar top surface;

forming a first masking layer over the substrate, wherein the first masking layer defines lateral boundaries for a transistor trench and an isolation trench;

applying a first anisotropic etch using the first masking layer as an etch mask to simultaneously form the transistor trench and the isolation trench in the substrate, wherein the transistor trench includes first and second opposing vertical sidewalls and a first bottom surface, the isolation trench includes third and fourth opposing vertical sidewalls and a second bottom surface, and the first and second bottom surfaces have essentially identical depths beneath the top surface;

stripping the first masking layer;

depositing a first oxide layer over the substrate so as to fill the trenches;

applying a second anisotropic etch to the first oxide layer to simultaneously form first and second oxide spacers adjacent to the first and second sidewalls, respectively, and third and fourth oxide spacers adjacent to the third and fourth sidewalls, respectively, such that a central portion of the first bottom surface between the first and second oxide spacers is exposed, and a central portion of the second bottom surface between the third and fourth oxide spacers is exposed;

simultaneously growing a gate oxide on the central portion of the first bottom surface and an oxide region on the central portion of the second bottom surface;

depositing a polysilicon layer over the substrate, on the first, second, third and fourth oxide spacers, and on the gate oxide and oxide region, so as to fill the trenches;

polishing the polysilicon layer until the polysilicon layer does not overlap the top surface and the polysilicon layer forms a polysilicon gate electrode in the transistor trench and a polysilicon region in the isolation trench, wherein the polysilicon gate electrode is electrically isolated from the substrate and substantially all of the polysilicon gate electrode is within the transistor trench;

forming a source and a drain in the substrate, wherein the source is adjacent to the first bottom surface and the first sidewall and the top surface, and the drain is adjacent to the first bottom surface and the second sidewall and the top surface;

providing a second masking layer over the substrate, wherein the second masking layer covers the transistor trench and exposes the isolation trench;

removing the polysilicon region from the isolation trench without removing the gate electrode from the transistor trench using the second masking layer as an etch mask;

stripping the second masking layer; and

depositing a second oxide layer over the substrate so as to fill the isolation trench with oxide.

22. The method of claim 21, wherein the first and second masking layers are photoresist layers.

23. The method of claim 21, including forming the source and the drain before depositing the second oxide layer over the substrate.

24. The method of claim 21, wherein a length between the first and second sidewalls is essentially identical to a length between the third and fourth sidewalls.

25. The method of claim 21, wherein the source and the drain define a channel adjacent to and beneath the first bottom surface, and a length of the channel is less than one-half of a length between the first and second sidewalls.