Programmable uniform symmetrical distribution logic allocator for a high-density complex PLD

• US 5,781,030 A
• Filed: 06/02/1995
• Issued: 07/14/1998
• Est. Priority Date: 06/02/1995
• Status: Expired due to Fees

• Current Assignee: Lattice Semiconductor Corporation
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Agrawal, Om P., Sharpe-Geisler, Bradley A.
• Primary Examiner(s): Westin, Edward P.
• Assistant Examiner(s): ROSEEN, RICHARD R
• Application Number:
  US08/459,234
• Time in Patent Office: 1,138 Days
• Field of Search: 326/38, 326/39, 326/41
• US Class Current: 326/39
• CPC Class Codes: H03K 19/1737 using multiplexers H03K19/1738 takes precedence
• CPC Class Codes: H03K 19/17704 the logic functions being realised by the interconnection of rows and columns
• CPC Class Codes: H03K 19/17744 for input/output signals

Abstract

A programmable uniform distribution logic allocator enhances the speed, silicon utilization, logic efficiency, logic utilization, and scalability of very high-density CPLDs including the logic allocator. The programmable uniform distribution logic allocator provides a uniform number of product terms to each I/O pin of the CPLDS and the same uniform number of product terms as feedback. However, no product terms are permanently connected to either a particular macrocell or a particular I/O pin. The programmable uniform distribution logic allocator includes a multiplicity of router elements where each router element steers a sum of a selected number of sum-of-product terms from a PAL structure, i.e, a selected number of logic product term-clusters, to a programmably selected logic macrocell. Specifically, the programmable uniform distribution logic allocator has a plurality of input lines, a plurality of output lines and a plurality of programmable router elements. Each programmable router element has an input terminal connected to an input line in the plurality of input lines and an output terminal connected to an output line in the plurality of output lines. Also, each programmable router element is programmably connectable to and disconnectable from each of input lines connected to the plurality of programmable router elements so that each output line has access to all input signals on the plurality of input lines.

Claims

1. In an integrated circuit, a programmable uniform distribution logic allocator comprising:

a plurality of N input lines where N is an integer;

a plurality of M output lines where M is an integer;

a first plurality of logic gates wherein each logic gate in said first plurality of logic gates includes;

a plurality of M/2 input terminals; and

an output terminal coupled to one output line in said plurality of M output lines;

a first plurality of programmable demultiplexers wherein each programmable demultiplexer includes;

an input terminal connected to an input line in said plurality of N input lines;

a plurality of M/2 output terminals wherein each output terminal in said plurality of M/2 output terminals is connected to an input terminal of a different logic gate in said first plurality of logic gates so that each output line coupled to one of said logic gates in said first plurality of logic gates has access to signals on each input terminal of said first plurality of programmable demultiplexers; and

said input terminal is programmably connectable to and disconnectable from said plurality of M/2 output terminals, and upon programmably connecting said input terminal to one of said plurality of M/2 output terminals, said input terminal is disconnected from all other output terminals in said plurality of M/2 output terminals;

a second plurality of logic gates wherein each logic gate in said second plurality of logic gates includes;

a plurality of M/2 input terminals; and

an output terminal coupled to one output line in said plurality of M output lines of said programmable uniform distribution logic allocator; and

a second plurality of programmable demultiplexers wherein each programmable demultiplexer includes;

an input terminal connected to an input line in said plurality of N input lines;

a plurality of M/2 output terminals wherein each output terminal in said plurality of M/2 output terminals is connected to an input terminal of a different logic gate in said second plurality of logic gates so that each output line coupled to one of said logic gates in said second plurality of logic gates has access to signals on each input terminal of said second plurality of programmable demultiplexers; and

said input terminal is programmably connectable to and disconnectable from said plurality of M/2 output terminals wherein upon programmably connecting said input terminal to one of said plurality of M/2 output terminals, said input terminal is disconnected from all other output terminals in said plurality of M/2 output terminals.

2. In an integrated circuit, a programmable uniform distribution logic allocator as in claim 1 wherein said integer N is equal to said integer M.

3. In an integrated circuit, a programmable uniform distribution logic allocator as in claim 1 wherein said integer N is sixteen.

4. In an integrated circuit, a programmable uniform distribution logic allocator as in claim 1 wherein said integer M is sixteen.

5. In an integrated circuit, a programmable uniform distribution logic allocator as in claim 1 further comprising:

a first plurality of exclusive-OR gates wherein each exclusive-OR gate in said first plurality of exclusive-OR gate has an input terminal connected to said output terminal of one logic gate in said first plurality of logic gates, and an output terminal connected to said output line in said plurality of M output lines, coupled to said output terminal of said one logic gate.

6. In an integrated circuit, a programmable uniform distribution logic allocator as in claim 1 wherein each logic gate output terminal is connected to one output line in said plurality of M output lines.

7. In an integrated circuit, a programmable uniform distribution logic allocator as in claim 5 further comprising:

a second plurality of exclusive-OR gates wherein each exclusive-OR gate, in said second plurality of exclusive OR gates, has an input terminal connected to said output terminal of one logic gate in said second plurality of logic gates, and an output terminal connected to said output line, in said plurality of M output lines, coupled to said output terminal of said one logic gate.