Programmable logic array

• US 5,781,031 A
• Filed: 11/21/1995
• Issued: 07/14/1998
• Est. Priority Date: 11/21/1995
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Cronin, John Edward, Bertin, Claude Louis
• Primary Examiner(s): SANTAMAURO, JON P
• Application Number:
  US08/560,250
• Time in Patent Office: 966 Days
• Field of Search: 326/38-41, 326/44-45, 257/777-778, 257/686, 365/189.08
• US Class Current: 326/39
• CPC Class Codes: H01L 2224/81899 using resilient parts in the bump connector or in the bonding area
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06593 Mounting aids permanently on device; arrangements for alignment
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H03K 19/17704 the logic functions being realised by the interconnection of rows and columns
• CPC Class Codes: H03K 19/1776 for memories
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

A programmable logic array (PLA) includes two direct-write EEPROM arrays, and PLA logic circuitry, such as feedback, drivers and input and output circuitry. One EEPROM array acts as an AND array and the other acts as n OR array. The PLA can be used for a memory function or a PLA function. In one aspect, the EEPROM arrays are placed on a first chip and the PLA logic circuitry a second chip. The first and second chips are stacked face-to-face, and force-responsive self-interlocking microconnectors are used to physically and electrically connect the separate chips. The separate chips are fabricated concurrently to reduce turn-around time.

Claims

1. A programmable logic array (PLA), comprising:

a plurality of memory cells and memory circuits, wherein said memory circuits allow operation of said memory cells for storage apart from said PLA, wherein said plurality of memory cells and memory circuits comprises;

a first memory array having a plurality of inputs, a plurality of outputs and being arranged in rows and columns, said first memory array acting as an AND array and said plurality of columns acting as product term lines;

a second memory array coupled to said first memory array having a plurality of inputs, a plurality of outputs and being arranged in rows and columns, said second memory array acting as an OR array and said plurality of columns acting as product term lines;

PLA logic circuitry coupled to at least some of said plurality of memory cells, said PLA logic circuitry comprising a plurality of inputs, a plurality of outputs, and a feedback connection between at least one of said plurality of outputs and at least one of said plurality of inputs; and

mode selection circuitry permitting operation of said plurality of memory cells as a memory apart from said PLA.

2. The PLA of claim 1 wherein said plurality of outputs comprises output logic.

3. The PLA of claim 1 wherein said plurality of outputs comprise a plurality of output latches.

4. The PLA of claim 1, wherein said memory cells each comprise a logic circuit and a flip flop.

5. The PLA of claim 1, wherein each of said plurality of memory cells is independently addressable, thereby allowing operation thereof for storage apart from said PLA.

6. The PLA of claim 1 wherein each of said plurality of memory cells comprises a transistor, a flip-flop controlling gate bias on said transistor, and a non-volatile transistor.

7. The PLA of claim 6, wherein each of said plurality of memory cells further comprises an additional transistor coupled to said transistor for sensing said transistor.

8. The PLA of claim 6, wherein each of said plurality of memory cells further comprises an additional transistor coupled to said flip-flop for setting a state of said flip-flop.

9. A programmable logic array (PLA), comprising:

a plurality of memory cells and memory circuits, wherein said memory circuits allow operation of said memory cells for storage apart from said PLA, and wherein said plurality of memory cells comprises a plurality of electrically erasable read only memory (EEPROM) cells; and

PLA logic circuitry coupled to at least some of said plurality of memory cells, said PLA logic circuitry comprising a plurality of inputs, a plurality of outputs, and a feedback connection between at least one of said plurality of outputs and at least one of said plurality of inputs.

10. The PLA of claim 9 wherein said plurality of EEPROM cells comprises a plurality of direct-write EEPROM cells.

11. A programmable logic array (PLA), comprising:

a plurality of memory cells and memory circuits, wherein said memory circuits allow operation of said memory cells for storage apart from said PLA; and

PLA logic circuitry coupled to at least some of said plurality of memory cells, said PLA logic circuitry comprising a plurality of inputs, a plurality of outputs, and a feedback connection between at least one of said plurality of outputs and at least one of said plurality of inputs, wherein said plurality of inputs comprises a plurality of bit partitioning input circuits.

12. A programmable logic array (PLA), comprising:

a plurality of memory cells and memory circuits, wherein said memory circuits allow operation of said memory cells for storage apart from said PLA;

PLA logic circuitry coupled to at least some of said plurality of memory cells, said PLA logic circuitry comprising a plurality of inputs, a plurality of outputs, and a feedback connection between at least one of said plurality of outputs and at least one of said plurality of inputs; and

a plurality of drivers for driving said plurality of memory cells.

13. A programmable logic array (PLA), comprising:

a plurality of memory cells and memory circuits, wherein said memory circuits allow operation of said memory cells for storage apart from said PLA, wherein each of said plurality of memory cells comprises a transistor and a flip-flop controlling gate bias on said transistor; and

PLA logic circuitry coupled to at least some of said plurality of memory cells, said PLA logic circuitry comprising a plurality of inputs, a plurality of outputs, and a feedback connection between at least one of said plurality of outputs and at least one of said plurality of inputs.

14. The PLA of claim 13, wherein each of said plurality of memory cells further comprises an additional transistor coupled to said transistor for sensing said transistor.

15. The PLA of claim 13, wherein each of said plurality of memory cells further comprises an additional transistor coupled to said flip-flop for setting a state of said flip-flop.

22. The PLA of claim 15, wherein said plurality of connectors comprise a plurality of metal bumps oppositely disposed on a facing surface of each said semiconductor chip, said PLA further comprising a means for connecting corresponding said oppositely disposed plurality of metal bumps, thereby providing both a physical and an electrical connection.

23. The PLA of claim 22, wherein said plurality of metal bumps comprise a plurality of gold bumps.

16. A programmable logic array (PLA), comprising:

a plurality of memory cells and memory circuits, wherein said plurality of memory cells reside on a first semiconductor chip; and

PLA logic circuitry coupled to at least some of said plurality of memory cells, said PLA logic circuitry comprising a plurality of inputs, a plurality of outputs, and a feedback connection between at least one of said plurality of outputs and at least one of said plurality of inputs, and wherein said PLA logic circuitry resides on a second semiconductor chip stackable with said first semiconductor chip, said PLA further comprising a plurality of connectors for connecting said first semiconductor chip and said second semiconductor chip.

17. The PLA of claim 16 wherein said plurality of connectors comprise a plurality of force-responsive self-interlocking microconnectors disposed on each of aid first semiconductor chip and said second semiconductor chip.

18. The PLA of claim 17 wherein said plurality of force-responsive self-interlocking microconnectors provide both a physical and an electrical connection between said first semiconductor chip and said second semiconductor chip.

19. The PLA of claim 17, wherein said plurality of connectors further comprise a plurality of repelling members disposed on one of said first semiconductor chip and said second semiconductor chip, said plurality of repelling members tending to push away a semiconductor chip coming into contact therewith, and said plurality of force-responsive self-interlocking microconnectors tending to pull said first semiconductor chip and said second semiconductor chip together, thereby providing a force-counter-force arrangement.

20. The PLA of claim 17, wherein said plurality of force-responsive self-interlocking microconnectors comprise a plurality of sizes providing differing alignment accuracy.

21. The PLA of claim 16, each of said first semiconductor chip and said second semiconductor chip further comprising at least one channel in which resides at least one of said plurality of connectors.

24. The PLA of claim 16 further comprising mode selection circuitry residing on one of said first semiconductor chip and said second semiconductor chip and permitting operation of said plurality of memory cells as a memory apart from said PLA.

25. The PLA of claim 16, wherein said plurality of outputs comprises output logic.

26. The PLA of claim 16, wherein said plurality of outputs comprises a plurality of output latches.

27. The PLA of claim 16 wherein each of said plurality of memory cells comprises a transistor and a flip-flop controlling gate bias on said transistor.

28. The PLA of claim 16 wherein each of said plurality of memory cells comprises a transistor, a flip-flop controlling gate bias on said transistor, and a non-volatile transistor.

29. A method of making a programmable logic array (PLA), comprising:

(a) providing a first memory array having a plurality of inputs, a plurality of outputs and being arranged in rows and columns, wherein said first memory array acts as an AND array, and wherein said plurality of columns act as product term lines;

(b) providing a second memory array having a plurality of inputs, a plurality of outputs and being arranged in rows and columns, wherein said second memory array acts as an OR array, and wherein said plurality of columns act as product term lines;

(c) programming said first memory array and said second memory array;

(d) electrically coupling said plurality of columns of said first memory array with said plurality of columns of said second memory array;

(e) providing PLA logic circuitry having a plurality of inputs and a plurality of outputs;

(f) electrically coupling at least one of said plurality of outputs of said PLA logic circuitry with at least one of said plurality of inputs of said PLA logic circuitry, thereby providing at least one feedback connection;

(g) electrically coupling at least some of said plurality of inputs of said first memory array with at least some of said plurality of inputs of said PLA logic circuitry;

(h) electrically coupling at least some of said plurality of outputs of said second memory array with at least some of said plurality of outputs of said PLA logic circuitry; and

(i) providing a plurality of memory circuits to allow operation of said first memory array and said second memory array for storage apart from said PLA.

30. The method of claim 29, wherein said first memory array comprises a first EEPROM memory array, wherein said second memory array comprises a second EEPROM memory array, and wherein said step (c) comprises programming said first EEPROM memory array and said second EEPROM memory array.

31. The method of claim 29 wherein said step (f) comprises electrically coupling through feedback circuitry.

32. The method of claim 29 wherein said steps (g) and (h) each comprise electrically coupling through a plurality of pass gates.

33. The method of claim 29, wherein each of said first memory array and said second memory array has independently addressable memory cells, thereby allowing operation thereof for storage apart from said PLA.

34. A method of making a programmable logic array (PLA), comprising:

(a) providing a first memory array having a plurality of inputs, a plurality of outputs and being arranged in rows and columns;

(b) providing a second memory array having a plurality of inputs, a plurality of outputs and being arranged in rows and columns, wherein said steps (a) and (b) comprise providing on a first semiconductor chip;

(c) programming said first memory array and said second memory array;

(d) electrically coupling said plurality of columns of said first memory array with said plurality of columns of said second memory array;

(e) providing PLA logic circuitry having a plurality of inputs and a plurality of outputs, and wherein said step (e) comprises providing on a second semiconductor chip;

(f) electrically coupling at least one of said plurality of outputs of said PLA logic circuitry with at least one of said plurality of inputs of said PLA logic circuitry, thereby providing at least one feedback connection;

(g) electrically coupling at least some of said plurality of inputs of said first memory array with at least some of said plurality of inputs of said PLA logic circuitry; and

(h) electrically coupling at least some of said plurality of outputs of said second memory array with at least some of said plurality of outputs of said PLA logic circuitry, said method further comprising steps of;

forming a plurality of connectors for connecting said first semiconductor chip and said second semiconductor chip; and

stacking said first semiconductor chip with said second semiconductor chip, wherein said first memory array acts as an AND array, wherein said plurality of columns act as product term lines, wherein said second memory array acts as an OR array, and wherein said plurality of columns act as product term lines.

35. The method of claim 34 wherein said steps (a), (b), (c) and (d) are performed concurrently with steps (e) and (f).

36. The method of claim 34 wherein said step of forming comprises forming a plurality of force-responsive self-interlocking microconnectors disposed on each of said first semiconductor chip and said second semiconductor chip.

37. The method of claim 36 wherein said plurality of force-responsive self-interlocking microconnectors provide both a physical and an electrical connection between said first semiconductor chip and said second semiconductor chip.

38. The method of claim 36 wherein said step of stacking comprises pressing said first semiconductor-chip together with said second semiconductor chip such that said plurality of force-responsive self-interlocking microconnectors interlock.

39. The method of claim 36 further comprising a step of forming at least one channel on each of said first semiconductor chip and said second semiconductor chip on which to form at least one of said plurality of force-responsive self-interlocking microconnectors.

40. The method of claim 34 wherein said step of forming comprises forming a plurality of metal bumps oppositely disposed on said first semiconductor chip and said second semiconductor chip.

41. The method of claim 40 wherein said step of stacking comprises providing a means for physically and electrically connecting said plurality of oppositely disposed metal bumps.

42. The method of claim 34, wherein said PLA logic circuitry resides on a face of said second semiconductor chip, wherein said first memory array and said second memory array reside on a face of said first semiconductor chip and wherein said step of stacking comprises stacking said first semiconductor chip and said second semiconductor chip.