Interrupt transmission via specialized bus cycle within a symmetrical multiprocessing system

• US 5,781,187 A
• Filed: 02/03/1997
• Issued: 07/14/1998
• Est. Priority Date: 05/31/1994
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Gephardt, Douglas, Mahalingaiah, Rupaka
• Primary Examiner(s): Harvey, Jack B.
• Assistant Examiner(s): WILEY, DAVID ARMAND
• Application Number:
  US08/794,526
• Time in Patent Office: 526 Days
• Field of Search: 395/308, 395/309, 395/306, 395/733-742
• US Class Current: 710/309
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: G06Q 40/128 Check-book balancing, updating or printing arrangements

Abstract

A symmetrical multiprocessing system is provided that includes centralized interrupt control unit. The interrupt control unit is coupled to a plurality of processing units and to a plurality of interrupt sources. The interrupt control unit advantageously allows for the expansion of each interrupt pin by setting the interrupt control unit in a cascade mode. Furthermore, the central control unit is responsive to specialized interrupt cycles which allows I/O devices and/or bus bridge devices to initiate of an interrupt without requiring a dedicated interrupt line. The central interrupt control unit further allows each interrupt to be prioritized independently of its associated vector ID, and prevents the occurrence of spurious interrupts by providing a programmable latency timer which causes the central interrupt control unit to delay its response to End Of Interrupt (EOI) instructions. An auto-chaining technique is further implemented by the central interrupt control unit to sequentially provide broadcast interrupts to various processing units based on their current task priority values. Finally, the central interrupt control unit further handles system management interrupts (SMIs) from sources such as power management units and ensures proper system operation even if the requested system management function affects operations being carried by other processing units.

Claims

1. A multiprocessing computer system, comprising:

a plurality of processing units coupled to a first bus;

first and second I/O devices coupled to a second bus;

a bus bridge coupling said first bus to said second bus and configured to selectively write data to said first and second I/O devices by executing I/O write cycles on a set of lines of said second bus; and

an interrupt controller coupled to said second bus and configured to process a first interrupt request signal received from said first I/O device coupled to said second bus, said interrupt request signal being conveyed on a dedicated interrupt signal line;

wherein said interrupt controller is further configured to receive a second interrupt request signal from said second I/O device, wherein said second interrupt request signal is conveyed as a predetermined encoded interrupt cycle driven upon said set of lines of said second bus.

2. The multiprocessing computer system of claim 1, wherein said second bus is configured to convey both interrupt related signals and non-interrupt related signals.

3. The multiprocessing computer system of claim 1, wherein said second bus is an expansion bus.

4. The multiprocessing computer system as recited in claim 1 wherein said encoded interrupt cycle on said set of lines of said second I/O bus is executed by said bus bridge.

5. The multiprocessing computer system as recited in claim 1 wherein said encoded interrupt cycle on said set of lines of said second I/O bus is executed by an interrupt controller coupled to said second I/O bus.

6. The multiprocessing computer system as recited in claim 1 wherein said second I/O bus is a PCI standard configuration bus, and said encoded interrupt cycle is defined by a pre-specified coding of a plurality of cycle definition bits of said PCI standard configuration bus.

7. The multiprocessing computer system as recited in claim 1 wherein said encoded interrupt cycle is defined as a cycle to a predetermined address in memory space of said multiprocessing computer system.

8. The multiprocessing computer system as recited in claim 1 wherein said encoded interrupt cycle is defined as a cycle to a predetermined address in I/O space of said multiprocessing computer system.

9. A multiprocessing computer system, comprising:

a plurality of processing units coupled to a first bus;

a second bus including a plurality of lines;

a bus bridge coupled between said first bus and said second bus;

an I/O device coupled to said second bus, wherein said bus bridge is configured to write data to said I/O device by executing an I/O write cycle upon said plurality of lines of said second bus; and

an interrupt controller coupled to said second bus and configured to receive an interrupt request from said I/O device, wherein said interrupt request is conveyed as a predetermined encoded interrupt cycle driven upon said plurality of lines of said second bus.

10. The multiprocessing computer system as recited in claim 9 wherein said encoded interrupt cycle on said second bus is executed by said bus bridge.

11. The multiprocessing computer system as recited in claim 9 wherein said encoded interrupt cycle on said second bus is executed by an interrupt controller coupled to said second bus.

12. The multiprocessing computer system as recited in claim 9 wherein said second bus is a PCI standard configuration bus, and said encoded interrupt cycle is defined by a pre-specified coding of a plurality of cycle definition bits of said PCI standard configuration bus.

13. The multiprocessing computer system as recited in claim 9 wherein said encoded interrupt cycle is defined as a cycle to a predetermined address in memory space of said multiprocessing computer system.

14. The multiprocessing computer system as recited in claim 9 wherein said encoded interrupt cycle is defined as a cycle to a predetermined address in I/O space of said multiprocessing computer system.