Interrupt transmission via specialized bus cycle within a symmetrical multiprocessing system
First Claim
1. A multiprocessing computer system, comprising:
- a plurality of processing units coupled to a first bus;
first and second I/O devices coupled to a second bus;
a bus bridge coupling said first bus to said second bus and configured to selectively write data to said first and second I/O devices by executing I/O write cycles on a set of lines of said second bus; and
an interrupt controller coupled to said second bus and configured to process a first interrupt request signal received from said first I/O device coupled to said second bus, said interrupt request signal being conveyed on a dedicated interrupt signal line;
wherein said interrupt controller is further configured to receive a second interrupt request signal from said second I/O device, wherein said second interrupt request signal is conveyed as a predetermined encoded interrupt cycle driven upon said set of lines of said second bus.
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Accused Products
Abstract
A symmetrical multiprocessing system is provided that includes centralized interrupt control unit. The interrupt control unit is coupled to a plurality of processing units and to a plurality of interrupt sources. The interrupt control unit advantageously allows for the expansion of each interrupt pin by setting the interrupt control unit in a cascade mode. Furthermore, the central control unit is responsive to specialized interrupt cycles which allows I/O devices and/or bus bridge devices to initiate of an interrupt without requiring a dedicated interrupt line. The central interrupt control unit further allows each interrupt to be prioritized independently of its associated vector ID, and prevents the occurrence of spurious interrupts by providing a programmable latency timer which causes the central interrupt control unit to delay its response to End Of Interrupt (EOI) instructions. An auto-chaining technique is further implemented by the central interrupt control unit to sequentially provide broadcast interrupts to various processing units based on their current task priority values. Finally, the central interrupt control unit further handles system management interrupts (SMIs) from sources such as power management units and ensures proper system operation even if the requested system management function affects operations being carried by other processing units.
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Citations
14 Claims
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1. A multiprocessing computer system, comprising:
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a plurality of processing units coupled to a first bus; first and second I/O devices coupled to a second bus; a bus bridge coupling said first bus to said second bus and configured to selectively write data to said first and second I/O devices by executing I/O write cycles on a set of lines of said second bus; and an interrupt controller coupled to said second bus and configured to process a first interrupt request signal received from said first I/O device coupled to said second bus, said interrupt request signal being conveyed on a dedicated interrupt signal line; wherein said interrupt controller is further configured to receive a second interrupt request signal from said second I/O device, wherein said second interrupt request signal is conveyed as a predetermined encoded interrupt cycle driven upon said set of lines of said second bus. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A multiprocessing computer system, comprising:
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a plurality of processing units coupled to a first bus; a second bus including a plurality of lines; a bus bridge coupled between said first bus and said second bus; an I/O device coupled to said second bus, wherein said bus bridge is configured to write data to said I/O device by executing an I/O write cycle upon said plurality of lines of said second bus; and an interrupt controller coupled to said second bus and configured to receive an interrupt request from said I/O device, wherein said interrupt request is conveyed as a predetermined encoded interrupt cycle driven upon said plurality of lines of said second bus. - View Dependent Claims (10, 11, 12, 13, 14)
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Specification