Parallel processing method for use with graphics processor

• US 5,781,199 A
• Filed: 11/14/1996
• Issued: 07/14/1998
• Est. Priority Date: 11/22/1995
• Status: Expired due to Term

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Yamane, Keisuke, Ozawa, Koji, Shiraishi, Masahiro, Kimura, Shinji, Oniki, Kazunori
• Primary Examiner(s): Tung, Kee M.
• Application Number:
  US08/749,193
• Time in Patent Office: 607 Days
• Field of Search: 345/505, 345/522, 345/506, 345/196
• US Class Current: 345/505
• CPC Class Codes: G06F 15/8007 single instruction multiple data [SIMD] multiprocessors

Abstract

A parallel processing method for use with a graphics processor wherein graphics processing is performed by each of configured command processors efficiently in a distributed manner, with a host CPU remaining unaware of the number of command processors. Each command group of a variable length from a host CPU is distributed from an FIFO queue to a plurality of parallelly arranged command processors for parallel processing through any free one of input FIFO queues corresponding to the command processors. Upon command group distribution, an identical serial number is added as a command group serial number to the commands constituting the same command group. The results of processing of individual graphics commands by the command processors are collected via output FIFO queues, which also correspond to the processors, in the order of the command group serial numbers added to the commands before the processed results are graphically drawn.

Claims

1. A parallel processing method for use with a graphics processor having a plurality of graphics command processors for parallelly processing a plurality of graphics commands from a host processor, said parallel processing method comprising the steps of:

distributing a command group made of said plurality of graphics commands via a first first-in-first-out queue to a second first-in-first-out queue corresponding to each of said plurality of graphics command processors arranged in parallel;

when said command group is distributed from said first first-in-first-out queue to said second first-in-first-out queues, adding an identical serial number as a command group serial number to each of said plurality of graphics commands constituting said command group to be processed by the command graphics processor corresponding to any second first-in-first-out queue which is found to be free in accordance with free status information about said second first-in-first-out queues;

collecting the results of processing of said graphics commands by said graphics command processors into a third first-in-first-out queue corresponding to each of said graphics command processors in the order of command group serial numbers added to the commands; and

drawing graphically the collected results of graphics command processing.

2. A parallel processing method for use with a graphics processor according to claim 1, further comprising the steps of:

performing a direct memory read operation of said collected results of graphics command processing held temporarily in said third first-in-first-out queues, when there occurs a coincidence between a value of a counter incremented by 1 every time a direct memory access read operation on any one of said third first-in-first-out queues has ended, on the one hand, and the command group serial number held by any one of said graphics command processors, on the other hand; and

reading said results of graphics command processing by each graphics command processor in the order of said command group serial numbers.

3. A parallel processing method for use with a graphics processor according to claim 2, further comprising the step of comparing the value of said counter and the command group serial number added to the command group output by said first first-in-first-out queue so as to keep within a predetermined count the number of command groups to be processed by said graphics command processors.