Tile memory mapping for increased throughput in a dual bank access DRAM
First Claim
1. A method of storing information into a dynamic random access memory, said dynamic random access memory having a plurality of memory arrays, individual memory arrays having a plurality of rows, and individual rows for storing pixel information, said method comprising the steps of:
- a) receiving sequential linear addresses of pixel information, said pixel information representing information for display on a display screen;
b) translating said linear addresses into physical addresses of a physical address space comprising arrays and rows of physical memory within said dynamic random access memory, wherein a central pixel stored in a given row of a given array has neighboring pixels on said display screen and wherein said step of translating comprises the step of assigning to said neighboring pixels only physical addresses comprising said given row of said given array or physical addresses comprising rows in arrays other than said given array; and
c) storing said pixel information into said dynamic random access memory using said physical addresses.
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Abstract
A method and apparatus for configuring memory within a dual access dynamic random access memory (DRAM) frame buffer so that array conflicts are reduced between neighboring pixels. The present invention DRAM frame buffer contains a number of arrays (e.g., 48), each array containing a number of rows (e.g., 256), each row contains a number of bytes (e.g., 1024). Rows of arrays are used to store frame buffer information within the DRAM. There is a single row of sense amplifiers per array, so rows of the same array conflict since they cannot be open at the same time. In an alternative embodiment, some neighboring arrays share the same row of sense amplifiers so neighboring arrays can conflict. The DRAM memory is configured such that for any given central pixel, its four spatially neighboring pixels (up, down, right and left) are not stored (1) in a different row of the same array as the central pixel nor (2) stored in a different row of any other conflicting array. Under this memory configuration, a row storing a neighboring pixel can be pre-opened with an activate memory access in the same cycle as a memory read/write access involving the central pixel, thus increasing memory access throughput. Particular memory configurations are given for screen displays of 640×480 (8/16/24 bpp), 800×600 (8/16/24 bpp), 1024×768 (8/16 bpp), and 1280×1024(8 bpp).
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Citations
19 Claims
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1. A method of storing information into a dynamic random access memory, said dynamic random access memory having a plurality of memory arrays, individual memory arrays having a plurality of rows, and individual rows for storing pixel information, said method comprising the steps of:
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a) receiving sequential linear addresses of pixel information, said pixel information representing information for display on a display screen; b) translating said linear addresses into physical addresses of a physical address space comprising arrays and rows of physical memory within said dynamic random access memory, wherein a central pixel stored in a given row of a given array has neighboring pixels on said display screen and wherein said step of translating comprises the step of assigning to said neighboring pixels only physical addresses comprising said given row of said given array or physical addresses comprising rows in arrays other than said given array; and c) storing said pixel information into said dynamic random access memory using said physical addresses. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. In a computer system having a processor coupled to a bus, a display screen coupled to said bus and a dynamic random access memory (DRAM) coupled to said bus wherein said DRAM having a plurality of memory arrays, individual memory arrays having a plurality of rows, and individual rows for storing pixel information, a method of accessing information regarding said DRAM, said method comprising the step of:
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a) receiving sequential linear addresses of pixel information, said pixel information representing information for display on a display screen; b) translating said linear addresses into physical addresses of a physical address space comprising arrays and rows of physical memory within said DRAM, wherein a central pixel stored in a given row of a given array has neighboring pixels and wherein said step of translating comprises the steps of; b1) assigning to ones of said neighboring pixels physical addresses comprising said given row of said given array; and b2) assigning to ones of said neighboring pixels physical addresses comprising rows in arrays other than said given array; and c) storing said pixel information into said DRAM using said physical addresses. - View Dependent Claims (14, 15, 16, 17, 18, 19)
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Specification