Tile memory mapping for increased throughput in a dual bank access DRAM

• US 5,781,200 A
• Filed: 08/08/1996
• Issued: 07/14/1998
• Est. Priority Date: 08/08/1996
• Status: Expired due to Term

• Current Assignee: Xylon LLC (Intellectual Ventures LLC)
• Original Assignee: ULSI Systems Co., Ltd.
• Inventors: Fan, Huei-Yi, Lu, Hsuehchung Shelton
• Primary Examiner(s): Kim, Matthew M.
• Assistant Examiner(s): CHAUHAN, ULKA J
• Application Number:
  US08/695,665
• Time in Patent Office: 705 Days
• Field of Search: 345/186, 345/188, 345/203, 345/507, 345/508, 345/509, 345/510, 345/515-517, 345/512, 711/105, 711/202, 711/203, 711/209
• US Class Current: 345/568
• CPC Class Codes: G09G 2360/126 The frame memory having additional data ports, not inclusive of standard details of the output serial port of a VRAM
• CPC Class Codes: G09G 5/39 Control of the bit-mapped memory
• CPC Class Codes: G11C 7/1015 Read-write modes for single port memories, i.e. having either a random port or a serial port
• CPC Class Codes: G11C 8/00 Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A method and apparatus for configuring memory within a dual access dynamic random access memory (DRAM) frame buffer so that array conflicts are reduced between neighboring pixels. The present invention DRAM frame buffer contains a number of arrays (e.g., 48), each array containing a number of rows (e.g., 256), each row contains a number of bytes (e.g., 1024). Rows of arrays are used to store frame buffer information within the DRAM. There is a single row of sense amplifiers per array, so rows of the same array conflict since they cannot be open at the same time. In an alternative embodiment, some neighboring arrays share the same row of sense amplifiers so neighboring arrays can conflict. The DRAM memory is configured such that for any given central pixel, its four spatially neighboring pixels (up, down, right and left) are not stored (1) in a different row of the same array as the central pixel nor (2) stored in a different row of any other conflicting array. Under this memory configuration, a row storing a neighboring pixel can be pre-opened with an activate memory access in the same cycle as a memory read/write access involving the central pixel, thus increasing memory access throughput. Particular memory configurations are given for screen displays of 640×480 (8/16/24 bpp), 800×600 (8/16/24 bpp), 1024×768 (8/16 bpp), and 1280×1024(8 bpp).

Claims

1. A method of storing information into a dynamic random access memory, said dynamic random access memory having a plurality of memory arrays, individual memory arrays having a plurality of rows, and individual rows for storing pixel information, said method comprising the steps of:

a) receiving sequential linear addresses of pixel information, said pixel information representing information for display on a display screen;

b) translating said linear addresses into physical addresses of a physical address space comprising arrays and rows of physical memory within said dynamic random access memory, wherein a central pixel stored in a given row of a given array has neighboring pixels on said display screen and wherein said step of translating comprises the step of assigning to said neighboring pixels only physical addresses comprising said given row of said given array or physical addresses comprising rows in arrays other than said given array; and

c) storing said pixel information into said dynamic random access memory using said physical addresses.

2. A method as described in claim 1 wherein said neighboring pixels comprise a first pixel directly above said central pixel, a second pixel directly below said central pixel, a third pixel directly to the right of said central pixel and a fourth pixel directly to the left of said central pixel.

3. A method as described in claim 1 further comprising the steps of:

d) accessing said given row of said given array of said dynamic random access memory to obtain pixel information for said central pixel; and

e) opening a row of an array of any one of said neighboring pixels, wherein said steps d) and e) are performed simultaneously.

4. A method as described in claim 1 wherein said step c) constructs a memory configuration for a screen display mode of 640 pixels horizontal by 480 pixels vertical with 8 bits per pixel and in said memory configuration, each horizontal display line of pixel information in a first set of display lines is stored in 5 rows across 5 arrays.

5. A method as described in claim 1 wherein said step c) constructs a memory configuration for a screen display mode of 640 pixels horizontal by 480 pixels vertical with 16 bits per pixel and in said memory configuration, each horizontal display line of pixel information in a first set of display lines is stored in 10 different rows wherein (1) eight of said ten rows are located in a set of arrays containing eight different arrays and (2) two of said ten rows are located in two arrays from said set of arrays.

6. A method as described in claim 1 wherein said step c) constructs a memory configuration for a screen display mode of 640 pixels horizontal by 480 pixels vertical with 16 bits per pixel and in said memory configuration, each horizontal display line of pixel information in a first set of display lines is stored in 15 different rows wherein (1) eight of said 15 rows are located in a set of arrays containing eight different arrays and (2) seven of said 15 rows are located in six arrays from said set of arrays.

7. A method as described in claim 1 wherein said step c) constructs a memory configuration for a screen display mode of 800 pixels horizontal by 600 pixels vertical with 8 bits per pixel and in said memory configuration, each horizontal display line of pixel information in a first set of display lines is stored in 6.25 rows spread across 7 different arrays.

8. A method as described in claim 1 wherein said step c) constructs a memory configuration for a screen display mode of 800 pixels horizontal by 600 pixels vertical with 16 bits per pixel and in said memory configuration, each horizontal display line of pixel information in a first set of display lines is stored in 12.5 rows wherein (1) eight of said 12.5 rows are located in a set of arrays containing eight different arrays and (2) 4.5 of said 12.5 rows are located in five arrays from said set of arrays.

9. A method as described in claim 1 wherein said step c) constructs a memory configuration for a screen display mode of 800 pixels horizontal by 600 pixels vertical with 24 bits per pixel and in said memory configuration, each horizontal display line of pixel information in a first set of display lines is stored in 18.75 rows.

10. A method as described in claim 1 wherein said step c) constructs a memory configuration for a screen display mode of 1024 pixels horizontal by 768 pixels vertical with 8 bits per pixel and in said memory configuration, each horizontal display line of pixel information in a first set of display lines is stored eight rows located in two different arrays.

11. A method as described in claim 1 wherein said step c) constructs a memory configuration for a screen display mode of 1024 pixels horizontal by 768 pixels vertical with 16 bits per pixel and in said memory configuration, each horizontal display line of pixel information in a first set of display lines is stored sixteen rows located in four different arrays.

12. A method as described in claim 1 wherein said step c) constructs a memory configuration for a screen display mode of 1280 pixels horizontal by 1024 pixels vertical with 8 bits per pixel and in said memory configuration, each horizontal display line of pixel information in a first set of display lines is stored in 12 rows wherein (1) eight of said 12 rows are located in a set of arrays containing eight different arrays and (2) four of said 12 rows are located in four arrays from said set of arrays.

13. In a computer system having a processor coupled to a bus, a display screen coupled to said bus and a dynamic random access memory (DRAM) coupled to said bus wherein said DRAM having a plurality of memory arrays, individual memory arrays having a plurality of rows, and individual rows for storing pixel information, a method of accessing information regarding said DRAM, said method comprising the step of:

a) receiving sequential linear addresses of pixel information, said pixel information representing information for display on a display screen;

b) translating said linear addresses into physical addresses of a physical address space comprising arrays and rows of physical memory within said DRAM, wherein a central pixel stored in a given row of a given array has neighboring pixels and wherein said step of translating comprises the steps of;

b1) assigning to ones of said neighboring pixels physical addresses comprising said given row of said given array; and

b2) assigning to ones of said neighboring pixels physical addresses comprising rows in arrays other than said given array; and

c) storing said pixel information into said DRAM using said physical addresses.

14. A method as described in claim 13 wherein said neighboring pixels comprise a first pixel directly above said central pixel, a second pixel directly below said central pixel, a third pixel directly to the right of said central pixel and a fourth pixel directly to the left of said central pixel.

15. A method as described in claim 13 further comprising the steps of:

d) accessing said given row of said given array of said DRAM to obtain pixel information for said central pixel; and

e) opening a row of an array of any one of said neighboring pixels, wherein said steps d) and e) are performed simultaneously.

16. A method as described in claim 13 wherein said step c) constructs a memory configuration for a screen display mode of 640 pixels horizontal by 480 pixels vertical with 8, 16 or 24 bits per pixel.

17. A method as described in claim 13 wherein said step c) constructs a memory configuration for a screen display mode of 800 pixels horizontal by 600 pixels vertical with 8 or 16 or 24 bits per pixel.

18. A method as described in claim 13 wherein said step c) constructs a memory configuration for a screen display mode of 1024 pixels horizontal by 768 pixels vertical with 8 or 16 bits per pixel.

19. A method as described in claim 13 wherein said step c) constructs a memory configuration for a screen display mode of 1280 pixels horizontal by 1024 pixels vertical with 8 bits per pixel.