Method for providing improved graphics performance through atypical pixel storage in video memory

• US 5,781,201 A
• Filed: 05/01/1996
• Issued: 07/14/1998
• Est. Priority Date: 05/01/1996
• Status: Expired due to Term

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Digital Equipment Corporation (HP Inc.)
• Inventors: McCormack, Joel J., Seiler, Larry D., Gianos, Christopher C., McNamara, Robert S.
• Primary Examiner(s): Kim, Matthew M.
• Assistant Examiner(s): CHAUHAN, ULKA J
• Application Number:
  US08/642,149
• Time in Patent Office: 804 Days
• Field of Search: 395/501-503, 395/507-510, 395/515-518, 395/520, 395/521, 395/523, 395/405, 395/481, 395/484, 395/495, 345/501-503, 345/507-510, 345/515-518, 345/520, 345/521, 345/523, 345/186-190, 345/188, 345/203, 345/200, 711/5, 711/154, 711/157, 711/168
• US Class Current: 345/544
• CPC Class Codes: G09G 2360/123 using interleaving
• CPC Class Codes: G09G 5/39 Control of the bit-mapped memory

Abstract

A method for improving the performance of a graphics system includes the steps of allocating appropriate pixels to slices of memory such that corresponding subsets of bits of neighboring pixels are allocated to different slices of memory, where `neighboring pixels` includes both consecutive pixels in a scan line, or pixels in consecutive scan lines. In addition, hardware is provided that allows for the individual memory slices to be independently accessed, thus allowed each slice to access data from a different 64 bit word in video memory during one video access period. Controllers which independently access the memory slices are advantageously totally time independent, to allow the most flexibility in the starting and finishing of the access of the memory slice. Performance is further gained by buffering of both the read and write requests to the video memory. Buffering requests allows reads and writes to neighboring locations to be merged to allow for the maximal bus utilization and minimizes the number of stalls in the video subsystem.

Claims

1. A method for improving the performance of a graphics system, said graphics system including a memory for storing an image comprising a plurality of pixels, said pixels comprising a plurality of subsets of bits of data, said memory comprising a plurality of slices, said method comprising the steps of:

storing said pixels in said memory, where a first order of the subsets of successive pixels is rearranged such that corresponding subsets of vertically and horizontally neighboring pixels are stored in different, simultaneously accessible locations of said memory.

2. The method according to claim 1, wherein each of said slices of said memory are independently controlled.

3. The method according to claim 1, wherein said step of storing includes the step of:

generating, by said graphics systems said plurality of pixels;

rearranging said first order of said subsets of each of said plurality of pixels; and

writing said rearranged subsets of pixels in said memory.

4. The method according to claim 1, further comprising the steps of:

reading said groups of subsets from said memory; and

restoring said subsets of each of said pixels to said first order.

5. A method for storing pixel data in a video memory, said video memory apportioned into a plurality of slices, said pixel data comprising a plurality of subsets of data for display on a CRT comprising a plurality of scan lines, said method comprising the steps of:

receiving data from a CPU coupled to said video memory, and converting said received data into a plurality of pixels each comprising a plurality of subsets of data;

rearranging an order of each of said subsets of each of said pixels; and

writing said pixels in said video memory, wherein the order of each of said subsets of pixels is rearranged such that corresponding subsets of vertically, horizontally, and diagonally neighboring pixels are stored in different, simultaneously accessible locations of said memory.

6. The method according to claim 5, wherein said pixels are rearranged by a determinable amount that is calculated responsive to a number of slices of said video memory.

7. The method according to claim 5, wherein rearranged subsets that require updating are temporarily stored in a buffer prior to said writing step.

8. The method according to claim 7, wherein each of said slices is allocated a respective buffer, and wherein each of said slices independently accesses data stored in its respective buffer for memory operations.

9. The method according to claim 5, further comprising the steps of:

reading, from said memory, said stored plurality of pixels;

storing said read plurality of pixels in a buffer; and

restoring said subsets of each of said pixels to said order.

10. An apparatus comprising:

means, responsive to control information from a central processor unit, for generating pixels, each of said pixels comprising a plurality of subsets of bits;

a memory for storing said generate d pixels, said memory apportioned into a plurality of slices, said pixels stored such that corresponding subsets of vertically and horizontally neighboring pixels stored in different, simultaneously accessible locations of said memory.

11. The apparat us of claim 10, further comprising:

means for rearranging an original order of said subsets of data of each of said pixels responsive to the number of slices of said memory;

means for writing said subsets of data in said rearranged order to said memory.

12. The apparatus of claim 11, further comprising:

a buffer for storing said rearranged data prior to writing said rearranged data to said memory.

13. The apparatus of claim 10, further comprising:

means for reading said rearranged pixel data from said memory; and

means for restoring said rearranged order of said subsets of data to said original order to provide said pixel data in a fixed byte order to said central processor unit.

14. The apparatus of claim 12, further comprising:

a buffer for storing data received from said memory during said read operation.

15. The apparatus of claim 10, further comprising:

a plurality of memory controllers, wherein there is one of said plurality of memory controllers for each one of said slices of said video memory, and wherein each of said memory controllers may independently address and control the associated slice of video memory;

a plurality of write buffers, corresponding to said plurality of memory controllers, each for storing a different portion of said subsets of data; and

means for selectively enabling each of said memory controllers to control the writing of said associated portion of said data stored in said write buffer to said corresponding slice of video memory.

16. The apparatus of claim 15, further comprising:

a plurality of read buffers, corresponding to said plurality of memory controllers, each one of said read buffers for storing pixel information from said memory slice corresponding to said associated memory controller; and

means for rearranging data received from said read buffers to provide pixel data in a fixed byte order to said central processing unit.

17. The apparatus of claim 10, wherein each pixel comprises four, eight bit subsets of data.

18. The apparatus of claim 10, wherein each pixel comprises two eight bit subsets of data.

19. The apparatus of claim 10, wherein said means for rearranging further comprises means for swapping the order of said subsets of data of said pixel.

20. The apparatus of claim 10, wherein said means for rearranging further comprises means for rotating the order of said subsets of data of said pixel.