Surge arrester

• US 5,781,393 A
• Filed: 04/16/1996
• Issued: 07/14/1998
• Est. Priority Date: 04/16/1996
• Status: Expired due to Fees

• Current Assignee: ERICO International Corporation (nVent Electric Plc)
• Original Assignee: ERICO International Corporation (nVent Electric Plc)
• Inventors: Glass, John C., Golonka, Kenneth A., DeGuire, Mark R., Tabib-Azar, Masood
• Primary Examiner(s): Gaffin, Jeffrey A.
• Assistant Examiner(s): SHERRY, MICHAEL JUDE
• Application Number:
  US08/633,204
• Time in Patent Office: 819 Days
• Field of Search: 361/56, 361/111, 361/117-130, 338/13, 338/20, 338/21, 338/22 R, 338/22 SD
• US Class Current: 361/118
• CPC Class Codes: H01T 4/10 having a single gap or a plurality of gaps in parallel

Abstract

A surge arrester which includes a pair of spaced metal electrodes and a semiconductor element interposed between the metal electrodes and in contact with at least one of the metal electrodes. The semiconductor element functions at least partially to bridge a gap between the metal electrodes with such gap serving as a current path between the metal electrodes in the event a voltage applied across the metal electrodes exceeds a firing voltage of the surge arrester. The semiconductor element includes a metal coating on at least a substantial portion of its outer surface which is in contact with the at least one metal electrode. The coating includes a gap between the electrodes and the gap may include a notch in the gap.

Claims

1. A surge arrester, comprising:

a pair of spaced metal electrodes; and

a semiconductor element interposed between the metal electrodes and in contact with at least one of the metal electrodes, the semiconductor element having a peripheral edge functioning at least to partially bridge a gap between the metal electrodes with such gap serving as a current path between the metal electrodes in the event a voltage applied across the metal electrodes exceeds a firing voltage of the surge arrester,

wherein the semiconductor element includes a metal coating on at least a substantial portion of its outer surface which is in contact with the at least one metal electrode, the metal coating extending generally parallel to the current path on the peripheral edge towards the gap.

2. The surge arrester of claim 1, wherein the metal coating comprises an electrically conductive metal.

3. The surge arrester of claim 1, wherein the metal coating includes at least one element selected from a group consisting of silver, chromium, platinum, palladium, copper and nickel, and alloys thereof.

4. The surge arrester of claim 1, wherein the semiconductor element metal coating is interposed between and in contact with both of the metal electrodes.

5. The surge arrester of claim 4, wherein the semiconductor element includes a gap surface which prevents a direct flow of current between the metal electrodes via the metal coating.

6. The surge arrester of claim 5, wherein the gap surface includes a notch in the semiconductor element.

7. The surge arrester of claim 6, wherein the notch is rectangular, circular or V-shape.

8. The surge arrester of claim 5, wherein the gap surface is formed by an absence of the metal coating.

9. The surge arrester of claim 4, wherein the semiconductor element comprises a ceramic disk and the metal electrodes each include a cylindrical cavity for receiving a respective portion of the ceramic disk in press fit relationship.

10. The surge arrester of claim 9, wherein the gap is formed by respective surfaces of the metal electrodes about the perimeter of the ceramic disk.

11. A surge arrester, comprising:

a pair of spaced metal electrodes; and

a semiconductor element interposed between the metal electrodes and in contact with at least one of the metal electrodes, the semiconductor element functioning at least to partially bridge a gap between the metal electrodes with such gap serving as a current path between the metal electrodes in the event a voltage applied across the metal electrodes exceeds a firing voltage of the surge arrester,

wherein the semiconductor element includes a metal coating on at least a substantial portion of its outer surface which is in contact with the at least one metal electrode, and

wherein the semiconductor element is in contact with only one of the metal electrodes and is electrically isolated from the other metal electrode.

12. The surge arrester of claim 11, wherein the semiconductor element comprises a ceramic disk and the one metal electrode include a cylindrical cavity for receiving a portion of the ceramic disk in press fit relationship.

13. The surge arrester of claim 11, wherein the gap is formed by respective surfaces of the metal electrodes about the perimeter of the ceramic disk.

14. A surge arrester, comprising:

a pair of spaced circular metal electrodes; and

a semiconductor disk in contact with and interposed between the metal electrodes, the semiconductor disk having a peripheral edge functioning to bridge a gap between the metal electrodes with such gap serving as a current path between the metal electrodes in the event a voltage applied across the metal electrodes exceeds a firing voltage of the surge arrester, and

wherein the semiconductor disk includes a metal coating on at least a substantial portion of its outer surface which is in contact with at least one of the metal electrodes, the metal coating extending generally parallel to the current path on the peripheral edge towards the gap.

15. The surge arrester of claim 14 wherein said metal coating is in intimate contact with both metal electrodes.

16. The surge arrester of claim 15, wherein the circumferential surface of the semiconductor disk bridges the gap between the metal electrodes and includes the metal coating, and such peripheral edge includes a gap which prevents a direct flow of current between the metal electrodes via the metal coating.

17. The surge arrester of claim 16, wherein the gap is formed by a notch in such surface.

18. The surge arrester of claim 17, wherein the notch is circular or rectangular.

19. The surge arrester of claim 17, wherein the notch is V-shape.

20. The surge arrester of claim 19, wherein said V-shape notch is a symmetrical combination of the annular gap in the coating and the annular gap between the electrodes.

21. A surge arrester, comprising:

pair of spaced circular metal electrodes; and

a semiconductor disk interposed between the metal electrodes with the semiconductor disk in contact with one of the metal electrodes and electrically isolated from the other metal electrode, the semiconductor disk functioning partially to bridge a gap between the metal electrodes with such gap serving as a current path between the metal electrodes in the event a voltage applied across the metal electrodes exceeds a firing voltage of the surge arrester, and

wherein the semiconductor disk includes a metal coating on at least a substantial portion of its outer surface which is in contact with the one metal electrode.

22. The surge arrester of claim 21, further comprising an insulating spacer interposed between the semiconductor disk and the other metal electrode.

23. A method of making a surge arrester comprising the steps of fitting two electrodes on opposite sides of a semiconductor disk, providing a conductive metal coating between at least one of said electrodes and said semiconductor disk, and producing a precision annular gap in said coating on a peripheral edge of said semiconductor disk between said electrodes.

24. A method as set forth in claim 23, including the step of providing such coating in intimate and complete contact between said semiconductor disk and said one electrode.

25. A method as set forth in claim 24, including recessing said semiconductor disk in said one electrode.

26. A method as set forth in claim 23, including the step of providing such coating in intimate and complete contact between said semiconductor disk and with both said electrodes.

27. A method as set forth in claim 26, including the step of providing the semiconductor disk with a girdling notch at said gap.

28. A method as set forth in claim 27, wherein said notch is pointed and symmetrical with the gap.

29. A method as set forth in claim 28, wherein said notch, coating gap and electrodes form a symmetrical annular flared gap.

30. A method as set forth in claim 23, wherein said conductive metal coating is provided on substantially the entire peripheral edge of the semiconductor disk except for the annular gap.