Method for producing integrated circuit chip having optimized cell placement
First Claim
1. A method for producing an integrated circuit chip having an optimized cell placement, comprising the steps of:
- (a) decomposing a placement optimization methodology into a plurality of cell placement optimization processes;
(b) performing said optimization processes simultaneously on input data representing said chip;
(c) recomposing results of said optimization processes and producing an optimized cell placement corresponding thereto;
(d) analyzing a fitness of said optimized cell placement;
(e) selectively repeating performing said optimization processes for further optimizing said optimized cell placement if said fitness does not satisfy a predetermined criterion;
(f) identifying low fitness areas of said optimized placement;
(g) selectively repeating performing said optimization processes on said low fitness areas respectively;
(h) generating a physical design of said integrated circuit chip embodying said optimized cell placement; and
(i) physically fabricating said integrated circuit chip in accordance with said physical design.
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Abstract
In a physical design automation system for producing an optimized cell placement for an integrated circuit chip, a placement optimization methodology is decomposed into a plurality of cell placement optimization processes that are performed simultaneously by parallel processors on input data representing the chip. The results of the optimization processes are recomposed to produce an optimized cell placement. The fitness of the optimized cell placement is analyzed, and the parallel processors are controlled to selectively repeat performing the optimization processes for further optimizing the optimized cell placement if the fitness does not satisfy a predetermined criterion. The system can be applied to initial placement, routing, placement improvement and other problems. The processors can perform the same optimization process on different placements, or on areas of a single placement. Alternatively, the processors can perform different optimization processes simultaneously on a single initial placement, with the resulting processed placement having the highest fitness being selected as the optimized placement. The processors can further selectively reprocess areas of a placement having high cell interconnect congestion or other low fitness parameters.
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Citations
17 Claims
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1. A method for producing an integrated circuit chip having an optimized cell placement, comprising the steps of:
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(a) decomposing a placement optimization methodology into a plurality of cell placement optimization processes; (b) performing said optimization processes simultaneously on input data representing said chip; (c) recomposing results of said optimization processes and producing an optimized cell placement corresponding thereto; (d) analyzing a fitness of said optimized cell placement; (e) selectively repeating performing said optimization processes for further optimizing said optimized cell placement if said fitness does not satisfy a predetermined criterion; (f) identifying low fitness areas of said optimized placement; (g) selectively repeating performing said optimization processes on said low fitness areas respectively; (h) generating a physical design of said integrated circuit chip embodying said optimized cell placement; and (i) physically fabricating said integrated circuit chip in accordance with said physical design. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method for producing an integrated circuit chip having an optimized cell placement, comprising the steps of:
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(a) decomposing a placement optimization methodology into a plurality of cell placement optimization processes; (b) performing said optimization processes simultaneously on input data representing said chip; (c) recomposing results of said optimization processes and producing an optimized cell placement corresponding thereto; (d) analyzing a fitness of said optimized cell placement; (e) selectively repeating performing said optimization processes for further optimizing said optimized cell placement if said fitness does not satisfy a predetermined criterion; (f) generating a physical design of said integrated circuit chip embodying said optimized cell placement; and (g) physically fabricating said integrated circuit chip in accordance with said physical design, in which; step (a) comprises generating a plurality of initial placements; step (b) comprises performing said cell optimization processes on said initial placements to produce a plurality of processed cell placements respectively; step (c) comprises designating a processed cell placement having a highest fitness as said optimized cell placement; and steps (b) and (e) each comprise performing said optimization processes as including genetic crossover between said initial placements.
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13. A method for producing an integrated circuit chip having an optimized cell placement, comprising the steps of:
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(a) decomposing a placement optimization methodology into a plurality of cell placement optimization processes; (b) performing said optimization processes simultaneously on input data representing said chip; (c) recomposing results of said optimization processes and producing an optimized cell placement corresponding thereto; (d) analyzing a fitness of said optimized cell placement; (e) selectively repeating performing said optimization processes for further optimizing said optimized cell placement if said fitness does not satisfy a predetermined criterion; (f) generating a physical design of said integrated circuit chip embodying said optimized cell placement; and (g) physically fabricating said integrated circuit chip in accordance with said physical design, in which; said optimization processes comprise different algorithms respectively; step (a) comprises generating an initial placement; step (b) comprises performing said cell optimization processes on said initial placement to produce a plurality of processed cell placements respectively; and step (c) comprises designating a processed cell placement having highest fitness as said optimized cell placement.
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14. A method for producing an integrated circuit chip having an optimized cell placement, comprising the steps of:
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(a) decomposing a placement optimization methodology into a plurality of cell placement optimization processes; (b) performing said optimization processes simultaneously on input data representing said chip; (c) recomposing results of said optimization processes and producing an optimized cell placement corresponding thereto; and (d) analyzing a fitness of said optimized cell placement; (e) selectively repeating performing said optimization processes for further optimizing said optimized cell placement if said fitness does not satisfy a predetermined criterion; (f) generating a physical design of said integrated circuit chip embodying said optimized cell placement; and (g) physically fabricating said integrated circuit chip in accordance with said physical design, in which; step (a) comprises the substeps of; (h) generating an initial placement; and (i) dividing cells of said initial placement into a plurality of nets of interconnected cells; and step (b) comprises performing said optimization processes on said nets respectively. - View Dependent Claims (15)
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16. A method for producing an integrated circuit chip having an optimized cell placement, comprising the steps of:
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(a) decomposing a placement optimization methodology into a plurality of cell placement optimization processes; (b) performing said optimization processes simultaneously on input data representing said chip; (c) recomposing results of said optimization processes and producing an optimized cell placement corresponding thereto; and (d) analyzing a fitness of said optimized cell placement; (e) selectively repeating performing said optimization processes for further optimizing said optimized cell placement if said fitness does not satisfy a predetermined criterion; (f) generating a physical design of said integrated circuit chip embodying said optimized cell placement; and (g) physically fabricating said integrated circuit chip in accordance with said physical design, in which; step (a) comprises the substeps of; (h) generating an initial placement; and (i) dividing cells of said initial placement into a plurality of groups of cells in accordance with a predetermined hierarchial organization; and step (b) comprises performing said optimization processes on said groups respectively. - View Dependent Claims (17)
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Specification