Merge/mask, rotate/shift, and boolean operations from two instruction sets executed in a vectored mux on a dual-ALU

• US 5,781,457 A
• Filed: 05/14/1996
• Issued: 07/14/1998
• Est. Priority Date: 03/08/1994
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Original Assignee: Exponential Technology, Inc.
• Inventors: Richter, David E., Cohen, Earl T., Blomgren, James S.
• Primary Examiner(s): Mai, Tan V.
• Application Number:
  US08/649,116
• Time in Patent Office: 791 Days
• Field of Search: 364/716.02, 364/716.01, 364/736.01
• US Class Current: 708/231
• CPC Class Codes: G06F 7/575 Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry
• CPC Class Codes: G06F 7/762 having at least two separately controlled rearrangement levels, e.g. multistage interconnection networks G06F7/764 - G06F7/768 take precedence
• CPC Class Codes: G06F 7/764 Masking

Abstract

A Boolean logic unit (BLU) features a vectored mux. Boolean instructions are executed by applying operands to the select inputs but truth-table signals to the data inputs. Merge and mask operations are performed by reversing the connection and inputting the operands to the data inputs but applying a merge mask to the select inputs. A byte-spreader copies byte or 16-bit operands to 32-bits before being rotated and merged by the vectored mux. A rotator is used to rotate an operand before being applied to the data input of the vectored mux so that compound rotate-merge operations can be executed in a single step through the vectored mux. A carry flag may also be merged in during a multi-step bit-test instruction. Complex CISC instructions such as rotate-through-carry and shift-double are executed in multiple steps on the vectored mux. Intermediate results are stored in the multiplier-quotient temporary registers which are normally used for multiply and divide instructions. A RISC ALU using the vectored mux BLU is modified only slightly to support execution of CISC instructions. Merge, mask, rotate, shift, and Boolean operations of both RISC and CISC instruction sets are executed in the same ALU because of the inherent flexibility of the vectored mux architecture.

Claims

1. A logic-instruction execution unit for executing Boolean operations and merge operations, the logic-instruction execution unit comprising:

a vectored mux for outputting a result of a Boolean operation or a merge operation, the vectored mux comprising a plurality of individual mux cells, each mux cell having data inputs and select control inputs and an output driving one bit-position of the result, the select control inputs controlling which data input is coupled to drive the output independently of other data inputs;

a first operand input comprising a plurality of electrical signals representing a first operand;

a second operand input comprising a plurality of electrical signals representing a second operand;

operand-spread means, receiving the first operand input, for extending the first operand from a reduced-width operand to a full-width operand by duplicating the reduced-width operand to fill bit-positions in a full-width operand beyond the reduced-width operand, the operand-spread means outputting a spread first operand to a first data input of the vectored mux when the first operand is a reduced-width operand;

Boolean control means for applying the first operand input and the second operand input to the select control inputs of the vectored mux when a Boolean operation is executed;

truth-table inputs comprising electrical signals representing at truth table for the Boolean operation, the truth-table inputs varying for different Boolean operations;

the Boolean control means including means for applying the truth-table inputs to the data inputs of the vectored mux when a Boolean operation is executed;

merge control means for applying the spread first operand to the first data input on the vectored mux and for applying the second operand input to a second data input on the vectored mux when a merge operation is executed;

a mask generator for generating a mask indicating a first portion of the result from the first operand and a second portion of the result from the second operand, the first portion and the second portion not overlapping;

the merge control means including means for applying the mask to a select control input of the vectored mux when a merge operation is executed, wherein the mask causes the vectored mux to select the first portion of the first operand applied to the first data input and the second portion of the second operand applied to the second data input,

whereby the vectored mux executes both merge operations and Boolean operations, the operands applied to the data inputs for merge operations but applied to the select control inputs for Boolean operations.

2. The logic-instruction execution unit of claim 1 wherein the reduced-width operand is a byte operand.

3. The logic-instruction execution unit of claim 1 wherein the operand-spread means is disabled for RISC instructions but enabled for CISC instructions using reduced-width operands.

4. The logic-instruction execution unit of claim 1 wherein the vectored mux is comprised of individual four-to-one mux cells each having four data inputs and two select control inputs;

the merge control means further comprising;

constant means for applying a constant electrical signal to one of the select control inputs when a mask or a merge operation is executed, the constant electrical signal preventing two of the four data inputs from being selected while allowing only the first and the second data inputs to be selected for mask and merge operations,

whereby the vectored mux uses four data inputs for Boolean operations of two operands but only two data inputs for mask and merge operations.

5. The logic-instruction execution unit of claim 4 further comprising:

rotate means, receiving the spread first operand, for rotating the spread first operand by a shift-count number of bit-positions and outputting a rotated first operand to the first data input of the vectored mux when a rotate operation is executed;

the merge control means applying the mask having a constant value when a simple rotate operation is executed, the constant value causing the rotated first operand to be selected to drive the output of the vectored mux as the result,

whereby rotate operations are also performed by the logic-instruction execution unit and rotate results are passed through the vectored mux.

6. The logic-instruction execution unit of claim 5 further comprising:

a carry flag indicating a carry from execution of a previous instruction;

the merge control means including carry means for applying the carry flag to the second data input on the vectored mux when a rotate-through-carry instruction is executed, the merge control means also applying the rotated first operand to the first data input on the vectored mux,

whereby the carry flag is merged in by the vectored mux.

7. The logic-instruction execution unit of claim 6 further comprising:

carry flag means, coupled to the rotate means, for generating as the carry flag the least-significant bit of the rotated first operand;

the carry means including means for applying a complement of the carry flag to the second data input on the vectored mux when a bit-test-and-complement instruction is executed, the merge control means also applying the first operand to the first data input on the vectored mux,

whereby the bit-test-and-complement instruction is executed by the vectored mux by merging the first operand with the complement of the carry flag.

8. The logic-instruction execution unit of claim 7 wherein the complement of the carry flag is applied to the second data input on the vectored mux during a subsequent cycle when a bit-test-and-complement instruction is executed, the rotate means rotating the spread first operand during an initial cycle before the subsequent cycle and outputting the least-significant bit of the rotated first operand to the carry flag means for generating the carry flag before the subsequent cycle, whereby the bit-test-and-complement instruction is executed in more than one cycle.

9. The logic-instruction execution unit of claim 7 for further executing a compound shift-merge instruction in a single step and a rotate-merge instruction in a single step, the merge control means applying the rotated first operand to the first data input and applying the mask to the select control input when the compound shift-merge instruction is executed.

10. The logic-instruction execution unit of claim 9 wherein the compound shift-merge instruction and rotate-merge instruction executed in a single step are each native RISC instructions and wherein the bit-test-and-complement instruction executed in more than one cycle is a native CISC instruction, whereby the vectored mux in the logic-instruction execution unit executes native RISC instructions and native CISC instructions.

11. The logic-instruction execution unit of claim 10 wherein the compound shift-merge instruction is a RISC rotate-left word immediate then mask-insert rlwimi instruction and wherein the bit-test-and-complement instruction is a CISC bit-test instruction.

12. A central processing unit (CPU) having an arithmetic-logic-unit (ALU) for executing integer instructions from a first instruction set and from a second instruction set, wherein the ALU comprises:

a first operand input;

a second operand input;

a byte-spreader for copying a byte-operand to a full width of the ALU;

a result output;

an adder for performing add and subtract operations on the first and second operand inputs, the adder outputting a sum as the result output;

a Boolean-logic unit for performing Boolean, merge, rotate, and shift operations, the Boolean-logic unit comprising;

a vectored mux having a plurality of multiplexer cells each having data inputs, a first select input and a second select input, and output for outputting one bit-position of the result output, each multiplexer cell selecting one of the data inputs as the result output in response to the first and second select inputs;

truth-table means for applying electrical signals representing a truth-table of a Boolean-logic function being executed to the data inputs of the vectored mux;

first select means for applying the second operand input to the first select inputs of the vectored mux when a Boolean operation is being executed, but applying a constant signal to the first select inputs when a Boolean operation is not being executed;

mask generator means for generating a mask indicating which bit-positions of the first operand input are output to the result output and which bit-positions of the first operand input are not output to the result output;

second select means for applying the first operand input to the second select inputs of the vectored mux when a Boolean operation is being executed, but applying the mask to the second select inputs when a Boolean operation is not being executed;

a shifter for shifting and rotating the first operand input to produce a shifted first operand when a rotate or shift operation is being executed;

first data select means, coupled to the shifter and the truth-table means, for outputting one of the truth-table signals to a data input of the vectored mux when a Boolean operation is being executed but for outputting the shifted first operand to a data input of the vectored mux when a Boolean operation is not being executed;

second data select means, coupled to the second operand input and the truth-table means, for outputting a second one of the truth-table signals to a second data input of the vectored mux when a Boolean operation is being executed but for outputting the second operand input to the second data input of the vectored mux when a Boolean operation is not being executed;

whereby the Boolean-logic unit executes Boolean-logic operations and merge, rotate, and shift operations.

13. The CPU of claim 12 wherein the Boolean, merge, rotate, and shift operations from the first instruction set are performed in a single clock cycle.

14. The CPU of claim 12 further comprising:

a first instruction decoder for decoding instructions from the first instruction set, the first instruction decoder generating decoded first instructions;

a second instruction decoder for decoding instructions from the second instruction set, the second instruction decoder generating decoded second instructions;

wherein the first instruction set has an encoding of instructions to operations which is independent of the encoding of instructions to operations for the second instruction set;

an instruction mux, for selecting decoded first instructions from the first instruction decoder when the CPU is executing instructions from the first instruction set but selecting decoded second instructions from the second instruction decoder when the CPU is executing instructions from the second instruction set;

a pipeline containing the ALU, the pipeline receiving the decoded instructions selected by the instruction mux;

wherein the ALU executes decoded first instructions from the first instruction set and decoded second instructions from the second instruction set.

15. The CPU of claim 14 wherein the instructions from the first instruction set are performed in a single clock cycle but compound instructions from the second instruction set are performed in two clock cycles, wherein the compound instructions from the second instruction set include a shift-double instruction and a rotate-through-carry instruction.

16. The CPU of claim 15 wherein the first instruction set is a RISC instruction set and wherein the second instruction set is a CISC instruction set.