Method and apparatus for switching data packets in a data network

• US 5,781,549 A
• Filed: 02/23/1996
• Issued: 07/14/1998
• Est. Priority Date: 02/23/1996
• Status: Expired due to Term

• Current Assignee: Allied Telesis Incorporated (Allied Telesis Holdings KK)
• Original Assignee: Allied Telesyn International'L Corporation
• Inventors: Dai, William
• Primary Examiner(s): Kizou, Hassan
• Assistant Examiner(s): BNIMOUSSA, ABDELHAMID
• Application Number:
  US08/603,576
• Time in Patent Office: 872 Days
• Field of Search: 370/300, 370/391, 370/392, 370/412, 370/413, 370/419, 370/422, 370/423, 370/364, 370/420, 370/398, 370/401, 370/476
• US Class Current: 370/398
• CPC Class Codes: H04L 12/5601 Transfer mode dependent, e.g. ATM
• CPC Class Codes: H04L 2012/5613 Bus (including DQDB)
• CPC Class Codes: H04L 2012/5615 Network termination, e.g. NT1, NT2, PBX
• CPC Class Codes: H04L 2012/5652 Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly
• CPC Class Codes: H04L 49/251 Cut-through or wormhole routing
• CPC Class Codes: H04L 49/255 Control mechanisms for ATM switching fabrics
• CPC Class Codes: H04L 49/3009 Header conversion, routing tables or routing tags
• CPC Class Codes: H04L 49/3081 ATM peripheral units, e.g. policing, insertion or extraction
• CPC Class Codes: H04L 49/351 for local area network [LAN], e.g. Ethernet switches

Abstract

A local area network switch which implements packet segmentation and reassembly for cell-based switching on a backplane cell bus. A plurality of packet processing units are each coupled to a backplane cell bus wherein each packet processing unit hosts a plurality of local area network ports. Each packet processing unit is associated with a single packet buffer memory that is shared by the ports associated with the packet processing unit. The segmentation of local area network packets into fixed-size cells facilitates an efficient local area network switch which provides dedicated bandwidth for each of the ports associated with the switch. There is also provision for coupling the local area network ports to communicate with a high-speed network interface.

Claims

1. A network data communication apparatus comprising:

a first port coupled to receive an incoming network data packet;

a data packet segmentation unit in communication with said first port for segmenting said incoming data packet into a plurality of fixed-size data cells;

a cell bus in communication with said data packet segmentation unit for conveying said fixed-sized data cells;

a data packet reassembly unit in communication with said cell bus for receiving said data cells and for reassembling said data cells into a network data packet;

a second port in communication with said data packet reassembly unit for transmitting said network data packet from said data communication apparatus;

a first additional plurality of ports each in communication with said data packet segmentation unit, said first additional plurality of ports coupled to receive incoming network data packets from a plurality of network source addresses;

a second additional plurality of ports each in communication with said data packet reassembly unit, said second additional plurality of ports coupled to transmit reassembled data packets to a plurality of network destination addresses;

a routing control unit in communication with said cell bus for monitoring data cell traffic on said cell bus and determining an output port(s) for network data packets, said routing control unit providing destination control packets for said data packet reassembly unit;

a routing table memory in communication with said routing control unit, said routing table memory for storing a data table of said network source addresses and the ports associated with said source addresses;

a control bus in communication with all of said ports of said network data communication apparatus for receiving port status data cells relating to activity associated with each of said ports;

a port status counter coupled to said control bus for accumulating said port status data cells;

an I/O bus;

bus bridging circuitry coupled between said I/O bus and said cell bus for conveying data traffic therebetween;

a high-speed network controller coupled to said I/O bus; and

a high-speed network interface coupled to said high-speed network controller for coupling said network data communication apparatus to a high-speed network.

2. The network data communication apparatus of claim 1 further comprising a microprocessor in communication with said I/O bus for handling network management protocols for said network data communication apparatus.

3. A network data communication apparatus comprising:

a first port coupled to receive an incoming network data packet;

a data packet segmentation unit in communication with said first port for segmenting said incoming data packet into a plurality of fixed-size data cells, said data packet segmentation unit comprising;

a data packet synchronizer for synchronizing a received data packet to a clock signal associated with said network data communication apparatus;

a cell header generator coupled to analyze said data packet for generating cell headers for data cells constituting said data packet, said cell header generator comprising;

a field classifier for classifying a field type of said data cell;

a byte counter for counting bytes in a data bit stream constituting said data packet;

a CRC checker operating on said data bit stream; and

a cell header register coupled to said field classifier, byte counter, and CRC checker for storing cell header bits responsive to each of said classifier, counter, and checker, respectively, said cell header bits for generating said cell headers;

a cell payload generator coupled to receive said data packet and divide it into fixed-size cell payloads for inclusion with said data cells on said cell bus;

a cell header and cell payload combiner in communication with said header generator and said payload generator for combining cell headers with cell payloads to generate data cells for transmission on said cell bus; and

cell transmission circuitry coupled to receive data cells from said combiner for transmission onto said cell bus;

a cell bus in communication with said data packet segmentation unit for conveying said fixed-sized data cells;

a data packet reassembly unit in communication with said cell bus for receiving said data cells and for reassembling said data cells into a network data packet;

a second port in communication with said data packet reassembly unit for transmitting said network data packet from said data communication apparatus;

a first additional plurality of ports each in communication with said data packet segmentation unit, said first additional plurality of ports coupled to receive incoming network data packets from a plurality of network source addresses; and

a second additional plurality of ports each in communication with said data packet reassembly unit, said second additional plurality of ports coupled to transmit reassembled data packets to a plurality of network destination addresses.

4. The network data communication apparatus of claim 3 wherein said cell payload generator comprises:

a serial-in/parallel-out (SIPO) register for serially receiving sequential bits of said data packet for outputting fixed-size cell payloads; and

a cell payload register coupled to said SIPO register for receiving and holding said fixed-size cell payloads.

5. The network data communication apparatus of claim 4 wherein said cell header and payload combiner comprises:

a cell transmission multiplexer coupled to said cell header register and said cell payload register for selecting a cell header and its corresponding cell payload; and

a bus output register coupled to said cell transmission multiplexer for holding a combined fixed-size data cell prior to transmission on said cell bus.

6. The network data communication apparatus of claim 5 wherein said cell transmission circuitry comprises:

a bus access controller for requesting cell bus access and for generating a transmission enable signal; and

a bus driver coupled to said bus output register and responsive to said transmission enable signal for conveying said data cell onto said cell bus.

7. The network data communication apparatus of claim 6 wherein said bus driver successively conveys first half of the fixed-size data cell then the rest of the fixed-size data cell onto said cell bus.

8. A network data communication apparatus comprising:

a first port coupled to receive an incoming network data packet;

a data packet segmentation unit in communication with said first port for segmenting said incoming data packet into a plurality of fixed-size data cells, said data packet segmentation unit comprising;

a data packet synchronizer for synchronizing a received data packet to a clock signal associated with said network data communication apparatus;

a cell header generator coupled to analyze said data packet for generating cell headers for data cells constituting said data packet;

a cell payload generator coupled to receive said data packet and divide it into fixed-size cell payloads for inclusion with said data cells on said cell bus;

a cell header and cell payload combiner in communication with said header generator and said payload generator for combining cell headers with cell payloads to generate data cells for transmission on said cell bus; and

cell transmission circuitry coupled to receive data cells from said combiner for transmission onto said cell bus;

a cell bus in communication with said data packet segmentation unit for conveying said fixed-sized data cells;

a data packet reassembly unit in communication with said cell bus for receiving said data cells and for reassembling said data cells into a network data packet, said data packet reassembly unit comprising;

packet assembly linked list control logic for directing the storage of cell data into a packet buffer memory, which is in communication with said data packet reassembly unit, for reassembly of said data packet; and

free linked list control logic for assigning blocks of memory in said packet buffer memory for storage of said data packet,

wherein the first block of memory for a given data packet is for storing information about the number of ports associated with said packet buffer memory said data packet is to be transmitted from;

a second port in communication with said data packet reassembly unit for transmitting said network data packet from said data communication apparatus;

a first additional plurality of ports each in communication with said data packet segmentation unit, said first additional plurality of ports coupled to receive incoming network data packets from a plurality of network source addresses; and

a second additional plurality of ports each in communication with said data packet reassembly unit, said second additional plurality of ports coupled to transmit reassembled data packets to a plurality of network destination addresses.

9. The network data communication apparatus of claim 8 further comprising media access control transmission logic in communication with said second port and said packet reassembly unit for directing transmission of said data packet from said packet buffer memory to said network, said transmission logic notifying said free linked list logic upon transmission of a packet for freeing blocks of memory in said packet buffer memory.

10. The network data communication apparatus of claim 9 wherein said media access control transmission logic initiates the transmission of a data packet prior to complete reassembly in accordance with a dynamically configurable cut-through transmission parameter.

11. A network switch comprising:

a first plurality of ports each for receiving and transmitting network data packets;

a first packet processing unit in communication with said first plurality of ports for segmenting data packets received from said first plurality of ports into fixed-size data cells and for reassembling fixed-size data cells into data packets for transmission from at least one of said first plurality of ports;

a first packet buffer memory coupled to said first packet processing unit for storing data packets as they are reassembled until they can be transmitted from at least one of said first plurality of ports;

a cell bus coupled to said first packet processing unit for conveying said data cells;

a second plurality of ports, each for receiving and transmitting network data packets;

a second packet processing unit coupled between said second plurality of ports and said cell bus, said second packet processing unit for segmenting data packets received on one of said second plurality of ports and for reassembling data packets to be transmitted from at least one of said second plurality of ports;

a switch packet routing control unit coupled to said cell bus for propagating control cells to said packet processing units for identifying which of said first and second plurality of ports said data packet is to be transmitted from, said routing control unit monitoring data cell traffic on said cell bus for associating ports with network addresses; and

a routing table memory coupled to said switch packet routing control unit for maintaining a table of network addresses associated with each of said first and second plurality of ports;

an I/O bus;

bus bridging circuitry coupled between said I/O bus and said cell bus for conveying data traffic therebetween;

a high-speed network controller coupled to said I/O bus; and

a high-speed network interface coupled to said high-speed network controller for coupling said network data communication apparatus to a high-speed network.

12. The network switch of claim 11 further comprising a microprocessor in communication with said I/O bus for handling network management protocols for said network switch.

13. A method of switching data packets in a network comprising the steps of:

receiving a data packet on a first network port;

segmenting said data packet into a plurality of fixed-size cells, including the steps of;

synchronizing the receipt of said data packet with an internal clock signal;

dividing the data packet into fixed-size cell payloads;

generating cell headers in accordance with an associated cell payload; and

combining a cell header with an associated cell payload to constitute a fixed-size cell;

propagating said fixed-size cells to a packet reassembly unit associated with a second network port, including the step of transmitting said fixed-size cells onto a cell bus;

reassembling said fixed-size cells into a reassembled network data packet, including the steps of;

receiving the fixed-size cells constituting a data packet; and

storing the cells in a packet buffer memory associated with said second network port in an order that reassembles the data packet, including the steps of;

allocating blocks of said packet buffer memory as needed for storage of said data packet;

maintaining a free pool of pointers to free memory blocks available for allocation in said packet buffer memory; and

tracking the number of output ports a data packet remains to be transmitted from;

transmitting said reassembled network data packet from said second network port; and

transmitting said reassembled network data packet from an additional plurality of network ports.

14. The method according to claim 13 wherein said transmitting said reassembled network data packet step comprises the steps of:

decrementing a counter value for the number of ports a packet remains to be transmitted from upon transmission of a data packet from one port; and

freeing blocks of said packet buffer memory associated with a data packet after said data packet has been transmitted from all its destination ports.

15. The method according to claim 14 further comprising the steps of:

each port reporting activity information; and

accumulating port activity information at a central location.