Packet receiving device

• US 5,781,599 A
• Filed: 09/06/1995
• Issued: 07/14/1998
• Est. Priority Date: 09/22/1994
• Status: Expired due to Term

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Shiga, Tomohisa
• Primary Examiner(s): Chin, Wellington
• Assistant Examiner(s): Corrielus, Jean B.
• Application Number:
  US08/524,214
• Time in Patent Office: 1,042 Days
• Field of Search: 375/354, 375/364, 375/373, 375/376, 375/355, 375/371, 375/327, 370/498, 370/503, 370/508, 370/509, 370/512, 370/516, 370/517, 348/518, 348/500, 358/425, 455/260
• US Class Current: 375/376
• CPC Class Codes: H04L 12/40058 Isochronous transmission
• CPC Class Codes: H04L 12/40117 Interconnection of audio or video/imaging devices home automation networks H04L12/2803; bitstream network arrangements specially adapted for distribution of digital video signals H04N7/24
• CPC Class Codes: H04N 21/4135 external recorder interface circuits between an apparatus for recording television signals and a television receiver H04N5/775
• CPC Class Codes: H04N 21/4223 Cameras H04N23/00 takes precedence
• CPC Class Codes: H04N 21/426 Internal components of the client ; Characteristics thereof H04N5/44 takes precedence
• CPC Class Codes: H04N 21/4305 Synchronising client clock from received content stream, e.g. locking decoder clock with encoder clock, extraction of the PCR packets arrangements for synchronising receiver with transmitter by comparing receiver clock with transmitter clock H04L7/0012; arrangements for synchronising receiver with transmitter wherein the receiver takes measures against momentary loss of synchronisation H04L7/0083
• CPC Class Codes: H04N 21/43632 involving a wired protocol, e.g. IEEE 1394 high-speed IEEE 1394 serial bus H04L12/40052
• CPC Class Codes: H04N 5/77 between a recording apparatus and a television camera
• CPC Class Codes: H04N 5/775 between a recording apparatus and a television receiver
• CPC Class Codes: H04N 7/54 the signals being synchronous H04N21/23602, H04N21/23614, H04N21/2365, H04N21/2368, H04N21/4341, H04N21/4342, H04N21/4347, H04N21/4348 take precedence

Abstract

An apparatus for receiving and decoding a packet of a multiplexed bit stream whose data is coded in a predetermined format, includes a temporary storage memory for compensating for the difference between the timing of the received packet and the read-in timing of the coded data by a decoder, counters and a comparison circuit for producing a clock signal which serves as a reference for operating the decoder on the basis of a reference signal in the predetermined format, and a calculation circuit for calculating the position of the reference signal using a time which is periodically added to the packet.

Claims

1. An apparatus for receiving and decoding a packet of a multiplexed bit stream whose data is coded to a predetermined format, comprising:

temporary storing means for compensating for the difference between the timing of the received packet and a read-in timing of the coded data to a decoder, wherein a data bit stream of a signal program extracted from the received packet is written in said temporary storing means, and wherein the data bit stream extracted from the received packet is supplied to the decoder through said temporary storing means;

means for producing a clock signal serving as a reference to operate the decoder on the basis of a reference signal in the predetermined format, wherein said means of producing a clock signal to operate the decoder has a single phase-locked-loop (PLL); and

means for calculating the position in time of the reference signal using a time which is periodically added to the packet, wherein said means for calculating the position in time of the reference signal comprises first means for calculating a time difference between the time of the reference signal from when it is transmitted and received on the basis of the position timing information in the predetermined format of the data extracted from the received packet and the periodical position timing information in the transmitted bit stream and second means for converting said time difference into the number of clock cycle signals in the transmission path.

2. The apparatus as claimed in claim 1, wherein said second means comprises a first counter for counting a clock signal of the data bit stream, a second counter for counting a clock signal in the transmission path, and a latch for latching the output value of said second counter when the time difference calculated by said first means coincides with the output value of said first counter.