Method and apparatus for extending the signal path of a peripheral component interconnect bus to a remote location

• US 5,781,747 A
• Filed: 11/14/1995
• Issued: 07/14/1998
• Est. Priority Date: 11/14/1995
• Status: Expired due to Term

• Current Assignee: Rateze Remote Mgmt. L.L.C. (Intellectual Ventures LLC)
• Original Assignee: Mesa Ridge Technologies, Inc. (iGo, Inc.)
• Inventors: Smith, Paul, Romascan, Edward
• Primary Examiner(s): Harvey, Jack B.
• Assistant Examiner(s): Lefkowitz, Sumati
• Application Number:
  US08/557,233
• Time in Patent Office: 973 Days
• Field of Search: 395/281-283, 395/822, 395/882-884, 395/892, 395/306-309
• US Class Current: 710/300
• CPC Class Codes: G06F 13/4045 where the bus bridge performs an extender function

Abstract

A peripheral component interconnect (PCI) extension/expansion system wherein the PCI Local Bus can be extended from a computer system'"'"'s motherboard to another location. A PCI translation card and remote PCI board communicate via a transmission medium to relay the signals from the PCI local bus to a remote location. The signals are then provided to remote expansion slots, where additional PCI components may be operated. Further, additional PCI connectors are provided for more add-in boards.

Claims

1. A system for extending a signal path of a host PCI bus comprising:

a first bus interface communicating with said host PCI bus, the first bus interface presenting only a single load to the host PCI bus;

a transmission medium having a first and second end, said first end electrically connected to said first bus interface;

a second bus interface electrically connected to said second end of said transmission medium; and

a second PCI bus communicating with said second bus interface, wherein the first bus interface comprises;

an expansion board;

a PCI bridge connected to said expansion board;

a primary bus having a primary bus signal connected to said PCI bridge;

a primary clock input connected so as to receive a clock signal from said host PCI bus;

a secondary bus electrically connected to receive said primary bus signal from said primary bus to generate a secondary bus signal; and

a secondary clock input connected so as to receive a delayed clock signal from said host PCI bus, wherein the secondary bus signal is the primary bus signal delayed by the delayed clock signal.

2. The system of claim 1 wherein the transmission medium is a copper wire cable.

3. The system of claim 1 wherein the transmission medium is a fiber optic cable.

4. The system of claim 1 wherein the transmission medium is a printed circuit board.

5. The system of claim 1 wherein the transmission medium is a pleated foil cable.

6. The system of claim 1 wherein the second bus interface comprises:

an expansion board;

a PCI bridge connected to said expansion board; and

a clock buffer connected so as to receive a clock signal from said PCI bridge.

7. The system of claim 1 further comprising a plurality of expansion slots mounted on a backplane, said second bus interface communicating with said second PCI bus via a remote PCI board.

8. The system of claim 7 wherein said expansion slots communicate with said second PCI bus.

9. The system of claim 7 wherein the signal path of the second PCI bus is extended to a second backplane.

10. The system of claim 1 further comprising:

a plurality of expansion slots mounted on a backplane, said second bus interface communicating with said second PCI bus via one of said expansion slots.

11. The system of claim 1, wherein the delay in the clock signal matches the transmission speed of the transmission medium.

12. A method of extending a signal path of a host PCI bus to a second PCI bus via a first bus interface having a first PCI bridge, a transmission medium, and a second bus interface having a second PCI bridge comprising the steps of:

(a) receiving a bus signal and a clock signal from said host PCI bus at said first bus interface, whereby said host PCI bus detects only a single load;

(b) delaying said clock signal an amount dependant on said transmission medium;

(c) transmitting said bus signal and said clock signal to said second bus interface via said transmission medium;

(d) receiving said signals at said second bus interface; and

(e) generating a PCI signal at said second bus interface.

13. The method of extending a signal path of a host PCI bus in claim 12 wherein said receiving and transmitting steps are accomplished using a PCI bridge.

14. A method of expanding a host PCI bus to a plurality of expansion slots mounted on a backplane, said expansion slots being electrically connected to a second PCI bus, wherein said second PCI bus communicates to said host bus via a first bus interface having a first PCI bridge, a transmission medium, and a second bus interface having a second PCI bridge comprising the steps of:

(a) receiving a bus signal and a clock signal from said host PCI bus at said first bus interface, whereby said host PCI bus detects only a single load;

(b) delaying said clock signal an amount dependant on said transmission medium;

(c) transmitting said bus signal and said clock signal to said second bus interface via said transmission medium;

(d) receiving said signals at said second bus interface;

(e) generating a PCI signal at said second bus interface; and

(f) communicating said PCI signal to said second PCI bus.

15. The method for expanding a host PCI bus in claim 14 wherein said receiving and transmitting steps are accomplished using a PCI bridge.