Graphics controller utilizing a variable frequency clock

• US 5,781,768 A
• Filed: 03/29/1996
• Issued: 07/14/1998
• Est. Priority Date: 03/29/1996
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Chips and Technologies, Inc. (Intel Corporation)
• Inventors: Jones, Morris E. Jr.
• Primary Examiner(s): Heckler, Thomas M.
• Application Number:
  US08/625,732
• Time in Patent Office: 837 Days
• Field of Search: 395/556
• US Class Current: 713/501
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 5/18 Timing circuits for raster scan displays specially adapted for television H04N ; synchronisation between the display unit and other display units, videodisc player G09G5/12

Abstract

The present invention includes a memory clock system for a graphics controller including a plurality of clock pulse generators, and a clock controller which selects the clock frequency based on the state of the graphics controller functional units.

Claims

1. A memory clock system for a graphics controller having functional units which includes:

a plurality of clock pulse generators, a clock controller including,

input lines having a state, said state being determined by the activity of said functional units,

clock control logic circuitry responsive to the state of said input lines,

an output signal line, said output signal line connected to each of said plurality of clock pulse generators wherein the clock control logic circuitry sends a signal on the output signal line, the signal indicating which of the clock pulse generators is to be active, whereby said clock controller causes said plurality of clock pulse generators to generate clock pulses at a predetermined frequency for use by the graphics controller based on the state of said functional units.

2. The clock system of claim 1 wherein the state of the input lines is further determined by the bandwidth requirements of the functional units.

3. A memory clock system for a graphics controller as recited in claim 1 wherein the functional units include a graphics accelerator engine, a CPU, and accessory function.

4. A memory clock system for a graphics controller as recited in claim 1 wherein the plurality of clock pulse generators includes a slow clock pulse generator and a fast clock pulse generator and wherein the clock control logic circuitry causes the slow clock pulse generator to generate clock pulses when at least one of the functional units is active and wherein the clock control logic circuitry causes the fast clock pulse generator to generate clock pulses when none of the functional units are active.

5. A memory clock system for a graphics controller having functional units which includes:

a variable clock pulse generator, a clock controller including,

input lines having a state, said state being determined by the activity of said functional units,

clock control logic circuitry responsive to the state of said input lines,

an output signal line, said output signal line connected to the variable clock pulse generator, wherein the clock control logic circuitry sends a signal on the output signal line the signal indicating a clock frequency to be generated by the variable clock pulse generator, whereby said clock controller causes said variable clock pulse generator to generate variable rate clock pulses for use by the graphics controller based on the state of said functional units.