Processor having operating modes for an upgradeable multiprocessor computer system

• US 5,781,774 A
• Filed: 09/03/1996
• Issued: 07/14/1998
• Est. Priority Date: 06/29/1994
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Krick, Robert F.
• Primary Examiner(s): Swann, Tod R.
• Assistant Examiner(s): Chow, Christopher S.
• Application Number:
  US08/711,318
• Time in Patent Office: 679 Days
• Field of Search: 395/282, 395/284, 395/651, 395/653
• US Class Current: 713/1
• CPC Class Codes: G06F 13/4072 Drivers or receivers G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002

Abstract

A processor for an upgradable system is disclosed having a type pin that indicates whether the processor is coupled as an OEM processor in a single processor or a dual processor computer system or as an upgrade processor in the dual processor computer system. The type pin causes the appropriate enable and disable of a cache coherency mechanism and a bus arbitration mechanism in the processor and coordination of a dual processor boot-up handshake.

Claims

1. A computer system for operating in a plurality of modes, including a dual processor mode, comprising:

a configurable processor including a central processing unit (CPU) type pin that receives a signal from the system, wherein a state of the signal causes the processor to be configured to operate as an original equipment manufacturer (OEM) processor or as an upgrade processor; and

a plurality of system control lines that couple the processor to another processor that is identical to the processor, wherein the processor is configured via the CPU type pin to operate as an OEM processor and said another processor is configured via its own CPU type pin to operate as an upgrade processor, including an identifying signal pin configured to transmit a signal identifying the presence of said another processor to the processor.

2. The computer system of claim 1, wherein the state of the signal received by the CPU type pin determines whether the processor has ownership of a system bus at startup of the system, wherein the system bus is common to the processor and to said another processor.

3. The computer system of claim 2, further comprising dual processor control circuitry coupled to the system control lines to sample the state of the signal received on the CPU type pin and, in response, to determine whether the processor operates in a dual processor mode or a single processor mode.

4. The computer system of claim 3, wherein the processor is further coupled to said another processor by a plurality of cache control lines and a plurality of arbitration lines and wherein the processor further comprises:

a bus arbitration mechanism coupled to the system bus and to the arbitration lines;

a cache coherency mechanism coupled to the cache control lines; and

a cache control circuit coupled to the cache coherency mechanism to receive a signal from said another processor on the identifying signal pin and, in response, to enable the bus arbitration mechanism and the cache coherency mechanism.

5. The computer system of claim 4, further comprising an interrupt identifier output transmitted to the system on the system bus, wherein when the dual processor control circuitry determines that the processor operates in a dual processor mode, the interrupt identifier output of the processor is changed to be an interrupt identifier different from an interrupt identifier of said another processor.

6. The computer system of claim 5, wherein when the dual processor control circuitry determines that the processor operates in a dual processor mode, communication over the plurality of system control lines is enabled.

8. The method of claim 2, further comprising the steps of:

sampling an interrupt identifier signal from the first processor and, in response, determining that the first processor is configured to operate as an OEM processor; and

sampling an interrupt identifier signal from the second processor and, in response, determining that the second processor is configured to operate as an upgrade processor.

9. The method of claim 8, further comprising the step of transmitting an identifying signal via the communication lines identifying the second processor to the first processor.

10. The method of claim 9, further comprising the steps of, in response to receipt of the identifying signal, enabling cache coherency and system bus arbitration mechanisms of the first processor.

11. The method of claim 10, further comprising the step of granting initial control of the system bus to the first processor.

7. A method for configuring a plurality of processors in a system to operate as an original equipment manufacturer (OEM) processor or as an upgrade processor, comprising the steps of:

transmitting a signal to a first processor of the plurality of processors on a central processing unit (CPU) type pin of the first processor to cause the first processor to be configured as an OEM processor;

transmitting a signal to a second processor of the plurality of processors on a CPU type pin of the second processor to cause the second processor to be configured as an upgrade processor; and

transmitting a plurality of signals directly from the first processor to the second processor via communication lines coupling the first processor and the second processor.

12. A configurable processor usable in a multiprocessor computer system, comprising:

a central processing unit (CPU) type pin configured to receive a configuration signal from the system, wherein the configuration signal causes the configurable processor to be configured to operate in an original equipment manufacturer (OEM) mode or an upgrade mode;

a plurality of interprocessor signal lines that carry a plurality of signals directly from the configurable processor to another processor;

processor core circuitry;

dual processor control circuitry coupled to the processor core circuitry and to the plurality of interprocessor signal lines;

a cache memory coupled to the processor core circuitry;

a cache control circuit coupled to the cache memory and to the plurality of interprocessor signal lines;

interrupt control circuitry coupled to the processor core circuitry and to the plurality of interprocessor signal lines; and

bus interface circuitry coupled to the cache control circuitry.

13. The configurable processor of claim 12, further comprising an identifying signal that is transmitted via the interprocessor signal lines, wherein when the identifying signal is received by the configurable processor, communication is enabled over the interprocessor signal lines between the configurable processor and another processor that transmitted the identifying signal.