Power management supply interface circuitry, systems and methods
First Claim
1. A personal computer comprising:
- an input device;
a memory;
a display;
a first integrated circuit having a microprocessor coupled to an input device, said memory, and said display;
a second integrated circuit coupled to said microprocessor having a power management logic circuit;
a first power supply connecter electrically coupled to said power management logic circuit and a second power supply connector electrically coupled to said power management logic circuit;
wherein said power management logic circuit comprises a first logic section connected to said first power supply connector, said first logic section having a suspend output, and a second logic section, having a suspend/resume switch input and a on switch input, and wherein a transistor is controlled by a voltage at a battery-dead terminal and is connected between both switches and a ground supply rail such that both switches are disconnected from said ground supply rail upon receipt of a battery-dead indication.
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Accused Products
Abstract
An electronic system (6) has a power management logic circuit (920). A first power supply connector (1902) is electrically coupled to the power management logic circuit (920) and a second power supply connector (1904) is also electrically coupled to the power management logic circuit (920). The power management logic circuit (920) has a first logic section (920A) connected to the first power supply connector (1902), and the first logic section (920A) has a suspend output (SUSPEND#). A second logic section (920B) is connected to the second power supply connector (1904) for operation independent of the first logic section (920A) when power is available at the second power supply connector (1904, . . . RTCPWR) and suspended at the first power supply connector (1902, VCC).
Other devices, systems and methods are also disclosed.
54 Citations
9 Claims
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1. A personal computer comprising:
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an input device; a memory; a display; a first integrated circuit having a microprocessor coupled to an input device, said memory, and said display; a second integrated circuit coupled to said microprocessor having a power management logic circuit; a first power supply connecter electrically coupled to said power management logic circuit and a second power supply connector electrically coupled to said power management logic circuit; wherein said power management logic circuit comprises a first logic section connected to said first power supply connector, said first logic section having a suspend output, and a second logic section, having a suspend/resume switch input and a on switch input, and wherein a transistor is controlled by a voltage at a battery-dead terminal and is connected between both switches and a ground supply rail such that both switches are disconnected from said ground supply rail upon receipt of a battery-dead indication. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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Specification