Method of forming a spacer

• US 5,783,475 A
• Filed: 11/20/1997
• Issued: 07/21/1998
• Est. Priority Date: 11/13/1995
• Status: Expired due to Term

• Current Assignee: Apple Inc.
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Ramaswami, Shrinath
• Primary Examiner(s): Bowers, Jr., Charles L.
• Assistant Examiner(s): Radomsky, Leon
• Application Number:
  US08/974,894
• Time in Patent Office: 243 Days
• Field of Search: 438/230-232, 438/303-307, 438/595
• US Class Current: 438/303
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

A method of forming a spacer (41) around a gate electrode (32) includes sequentially disposing a first layer (48), a second layer (36), and a third layer (37) of dielectric over a semiconductor substrate (31) and over the gate electrode (32) and, thereafter, sequentially etching the third (37), second (36), and first (48) layers. The third layer (37) is etched with a first etchant to define a width (51) for the spacer (41). The first etchant selectively etches the third layer (37) versus the second layer (36). Etching the third layer (37) does not expose the first layer (48) located beneath the second layer (36). A second etchant, which is different from the first etchant, is used to selectively etch the second layer (36) versus the first layer (48). Etching the second layer (36) does not expose the semiconductor substrate (31) located beneath the first layer (48).

Claims

1. A method of making a semiconductor component, the method comprising the steps of:

providing a semiconductor substrate;

fabricating a gate electrode over the semiconductor substrate;

disposing a first layer comprised of a first dielectric material over the semiconductor substrate and adjacent to the gate electrode;

disposing a second layer comprised of a second dielectric material over the first layer;

disposing a third layer comprised of the first dielectric material over the second layer;

anisotropically removing a first portion of the third layer with a first etchant, wherein a portion of the third layer remains over a portion of the second layer;

removing a second portion of the second layer with a second etchant different from the first etchant to form a portion of a spacer; and

simultaneously removing a third portion of the first layer and the portion of the third layer to expose the portion of the second layer and to expose a portion of the semiconductor substrate.

2. The method according to claim 1, wherein the steps of disposing the first and third layers includes disposing silicon oxide and wherein the step of disposing the second layer includes disposing silicon nitride.

3. The method according to claim 2, wherein the step of disposing the first layer includes thermally growing the first layer on the semiconductor substrate and wherein the steps of disposing the second and third layers includes using a chemical vapor deposition.

4. The method according to claim 1, further comprising the step of implanting a lightly doped source region and a lightly doped drain region into the semiconductor substrate after the step of disposing the first layer.

5. The method according to claim 4, further comprising the step of implanting a source region and a drain region into the semiconductor substrate after the step of removing the second portion of the second layer.

6. The method according to claim 1, wherein the step of anisotropically removing the first portion of the third layer includes defining a width for the spacer.

7. The method according to claim 1, wherein the step of anisotropically removing the first portion of the third layer includes selectively etching the third layer versus the second layer, wherein the step of removing the second portion of the second layer includes isotropically etching and selectively etching the second portion of the second layer versus the first layer, and wherein the step of removing the third portion of the first layer includes isotropically etching and selectively etching the third portion of the first layer versus the semiconductor substrate.

8. The method according to claim 1, wherein the step of removing the third portion of the first layer includes exposing a fourth portion of the semiconductor substrate and a fifth portion of the gate electrode.

9. The method according to claim 8, further including the step of forming a silicide in the fourth portion of the semiconductor substrate and in the fifth portion of the gate electrode.

10. A method of fabricating a semiconductor component, the method comprising the steps of:

providing a substrate having a feature;

sequentially providing a first layer, a second layer, and a third layer over the substrate and adjacent to the feature; and

forming a spacer adjacent to the feature by sequentially etching the third layer, the second layer, and the first layer, wherein etching the third layer uses a first etchant to selectively etch the third layer over the second layer and leaves a portion of the third layer overlying the second layer, wherein etching the second layer uses a second etchant different from the first etchant to selectively etch the second layer over the first layer, and wherein etching the first layer exposes a portion of the substrate and removes the portion of the third layer.

11. The method according to claim 10, wherein the step of sequentially providing the first, second, and third layers includes:

thermally growing a first oxide layer over the substrate;

depositing a nitride layer over the first oxide layer; and

depositing a second oxide layer over the nitride layer.

12. The method according to claim 11, further comprising the step of providing a gate electrode for the feature, wherein the step of thermally growing the first oxide layer includes oxidizing the gate electrode.

13. The method according to claim 10, wherein the step of forming the spacer includes:

anisotropically etching the third layer with the first etchant to expose a first portion of the second layer; and

etching the first portion of the second layer with the second etchant to expose a second portion of the first layer.

14. The method according to claim 13, wherein the step of forming the spacer further includes etching the second portion of the first layer with a third etchant different from the first and second etchants wherein the step of sequentially providing the first, second, and third layers includes providing oxide for the first and third layers.

15. A method of fabricating a semiconductor device, the method comprising the steps of:

providing a semiconductor substrate;

forming a gate electrode over the semiconductor substrate;

oxidizing the gate electrode, wherein oxidizing the gate electrode grows a first oxide layer over the semiconductor substrate and adjacent to and over the gate electrode;

depositing a nitride layer over the first oxide layer;

depositing a second oxide layer over the nitride layer;

anisotropically etching the second oxide layer to expose a first portion of the nitride layer;

overetching the second oxide layer with a first etchant, wherein the overetching etches the nitride layer and leaves a portion of the second oxide layer over a portion of the nitride layer;

etching the first portion of the nitride layer to expose a second portion of the first oxide layer, wherein etching the first portion of the nitride layer uses an etchant different from the first etchant; and

simultaneously etching the second portion of the first oxide layer and the portion of the second oxide layer to expose a third portion of the semiconductor substrate, a fourth portion of the gate electrode, and the portion of the nitride layer.

16. The method according to claim 15, further comprising the steps of:

implanting a lightly doped source region and a lightly doped drain region self-aligned to the gate electrode after the step of oxidizing the gate electrode and before the step of depositing the nitride layer; and

implanting a source region and a drain region self-aligned to the spacer after the step of etching the first portion of the nitride layer and before the step of etching the second portion of the first oxide layer.

17. The method according to claim 15, further including the step of forming a silicide contact in the third portion of the semiconductor substrate and in the fourth portion of the gate electrode after the step of etching the second portion of the first oxide layer.

18. The method according to claim 15, wherein the step of etching the first portion of the nitride layer includes isotropically etching the first portion of the nitride layer and wherein the step of etching the second portion of the first oxide layer includes isotropically etching the second portion of the first oxide layer.

19. The method according to claim 18, wherein the step of isotropically etching the first portion of the nitride layer includes using phosphoric acid and wherein the step of isotropically etching the second portion of the first oxide layer includes using hydrofluoric acid.

20. The method according to claim 15, wherein the step of depositing the second oxide layer includes using tetraethyl orthosilicate.