Method for bonding compounds semiconductor wafers to create an ohmic interface

• US 5,783,477 A
• Filed: 04/14/1997
• Issued: 07/21/1998
• Est. Priority Date: 09/20/1996
• Status: Expired due to Term

• Current Assignee: Lumileds LLC (Apollo Global Management, Inc.)
• Original Assignee: Hewlett-Packard Company (HP Inc.)
• Inventors: Kish, Fred A. Jr., Vanderwater, David A.
• Primary Examiner(s): Bowers, Jr., Charles L.
• Assistant Examiner(s): Thompson, Craig
• Application Number:
  US08/835,948
• Time in Patent Office: 463 Days
• Field of Search: 438/455, 438/456, 438/457, 438/458, 438/459
• US Class Current: 438/455
• CPC Class Codes: H01L 21/187 by direct bonding
• CPC Class Codes: H01L 2924/12041 LED
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate

Abstract

A method for forming an ohmic interface between unipolar (isotype) compound semiconductor wafers without a metallic interlayer and the semiconductor devices formed with these ohmic interfaces are disclosed. The ohmic interface is formed by simultaneously matching the crystallographic orientation of the wafer surfaces and the rotational alignment within the surfaces of the two wafers and then subjecting them to applied uniaxial pressure under high temperatures to form the bonded ohmic interface. Such an ohmic interface is required for the practical implementation of devices wherein electrical current is passed from one bonded wafer to another.

Claims

1. A method for bonding at least two semiconductor surfaces to form a bonded interface that exhibits low electrical resistance with a minimal accompanying voltage drop, at least one of the surfaces being bonded comprising a compound semiconductor, the two surfaces having similar doping types, the method comprising the steps of:

heating the two semiconductor surfaces;

aligning the surface orientation of the two semiconductor surfaces;

aligning the rotational alignment of the two semiconductor surfaces; and

applying uniaxial pressure to the heated, oriented and aligned surfaces.

2. The method of claim 1 wherein the steps of heating, matching the surface orientation, aligning the rotational alignment, and applying uniaxial pressure may occur in any order.

3. The method of claim 1 wherein the magnitude of the difference between the surfaces'"'"' orientations is less than 6 degrees and the magnitude of the difference between the surfaces'"'"' rotational alignments is less than 20 degrees.

4. The method of claim 3 wherein the steps of matching the surface orientation and aligning the rotational alignment are relaxed to include crystallographically equivalent directions in the crystal structures of the semiconductor surfaces.

5. The method of claim 3 wherein at least one of the semiconductor surfaces comprises In_x (Al_w Ga_1-w)_1-x P, where x has a value of from 0 to 1 and w has a value from 0 to 1.

6. The method of claim 5 wherein the second bonding surface comprises In_y (Al_z Ga_1-z)_1-y P, where y has a value of from 0 to 1 and z has a value of from 0 to 1.

7. The method of claim 2 wherein both surfaces are p-type.

8. The method of claim 2 wherein both surfaces are n-type.

9. The method of claim 6 wherein at least one of the at least two semiconductor surfaces has patterned areas of one of the group of materials including amorphous and polycrystalline semiconductors, bonding of the patterned surface and the second semiconductor surface forming areas of ohmic and non-ohmic conduction.

10. The method of claim 1 wherein the two semiconductor surfaces are heated to a temperature within the range of 200°

to 1,100°

C.

11. The method of claim 1 wherein the two semiconductor surfaces have a similar crystal structure.

12. The method of claim 10 wherein the two semiconductor surfaces are heated to a temperature within the range of 700°

to 1,000°

C.

13. The method of claim 4 wherein the at least two semiconductor surfaces have dissimilar crystal structures with the crystal structures having the same atomic arrangement within a geometric scaling factor.

14. The method of claim 7 wherein the doping level of the p-type surfaces is increased to at least 3×

10⁷ cm^-3 to minimize the resistance across the interface.

15. The method of claim 8 wherein the doping level of the n-type surfaces is increased to at least 3×

10¹⁷ cm^-3 to minimize the resistance across the interface.