Multilevel interconnect structure of an integrated circuit having air gaps and pillars separating levels of interconnect

• US 5,783,864 A
• Filed: 06/05/1996
• Issued: 07/21/1998
• Est. Priority Date: 06/05/1996
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Dawson, Robert, Michael, Mark W., Brennan, William S., Fulford, H. Jim Jr., Bandyopadhyay, Basab, Hause, Fred N.
• Primary Examiner(s): Hardy, David B.
• Application Number:
  US08/655,248
• Time in Patent Office: 776 Days
• Field of Search: 257/522, 257/508, 257/664, 257/734, 257/750, 257/773, 257/774, 257/776, 428/421, 428/422
• US Class Current: 257/758
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An improved multilevel interconnect structure is provided. The interconnect structure includes pillars spaced from each other across a wafer. The pillars are placed between levels of interconnect or between an interconnect level and a semiconductor substrate. The pillars are spaced from each other by an air gap, such that each conductor within a level of interconnect is spaced by air from one another. Furthermore, each conductor within one level of interconnect is spaced by air from each conductor within another level of interconnect. Air gaps afford a smaller interlevel and intralevel capacitance within the multilevel interconnect structure, and a smaller parasitic capacitance value affords minimal propagation delay and cross-coupling noise of signals sent through the conductors. The air gaps are formed by dissolving a sacrificial dielectric, and the conductors are prevented from bending or warping in regions removed of sacrificial dielectric by employing anodization on not just the upper surfaces of each conductor, but the sidewalls as well. The upper and sidewall anodization provides a more rigid metal conductor structure than if merely the upper or sidewall surfaces were anodized. Accordingly, the pillars can be spaced further apart and yet provide all necessary support to the overlying conductors.

Claims

1. A multilevel interconnect structure, comprising:

a first layer of dielectric pillars spaced by air from each other across a semiconductor topography;

a first layer of substantially coplanar conductors spaced by air from each other across the upper ends of said first layer of dielectric pillars; and

a first contact configured within a select one of said dielectric pillars, wherein said contact extends perpendicular to said semiconductor topography from said semiconductor topography to one conductor within said first layer of conductors.

2. The multilevel interconnect structure as recited in claim 1, wherein said dielectric pillars comprise nitride.

3. The multilevel interconnect structure as recited in claim 1, wherein said contact is configured entirely within a lateral perimeter of said dielectric pillar.

4. The multilevel interconnect structure as recited in claim 1, wherein said first layer of dielectric pillars are substantially coplanar to each other at an elevational level below the first layer of conductors.

5. The multilevel interconnect structure as recited in claim 1, further comprising:

a second layer of dielectric pillars spaced by air from each other across the first layer of conductors;

a second layer of substantially coplanar conductors spaced by air from each other across the upper ends of said second layer of dielectric pillars; and

a second contact configured within a select one of said dielectric pillars, wherein said contact extends perpendicular to said first layer of conductors from said first layer of conductors to one conductor within said second layer of conductors.