CMOS current controlled delay element using cascoded complementary differential amplifiers with replicated bias clamp
First Claim
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1. A circuit connected between a high potential source and a low potential source, the circuit comprising:
- a first differential amplifier connected to first and second input nodes to receive first and second input signals, and connected to first and second output nodes for supplying first and second output signals;
a second differential amplifier connected to the first and second input nodes to also receive the first and second input signals, and connected to first and second output nodes for also supplying the first and second output signals;
a first transistor having a control electrode coupled to receive a first bias signal, the first transistor coupled between the first differential amplifier and the high potential source;
a second transistor having a control electrode coupled to receive a second bias signal, the second transistor coupled between the second differential amplifier and the low potential source;
a first clamp circuit coupled between the first input node and the first output node; and
a second clamp circuit coupled between the second input node and the second output node.
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Abstract
A cascoded cmos differential delay element is described. The delay element provides a controlled delay useful in forming voltage controlled oscillators or other circuits. The delay element provides high gain enabling it to be useful in multistage delay element circuits. The circuit described includes cascoded complementary differential amplifiers and replicated bias clamps.
16 Citations
11 Claims
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1. A circuit connected between a high potential source and a low potential source, the circuit comprising:
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a first differential amplifier connected to first and second input nodes to receive first and second input signals, and connected to first and second output nodes for supplying first and second output signals; a second differential amplifier connected to the first and second input nodes to also receive the first and second input signals, and connected to first and second output nodes for also supplying the first and second output signals; a first transistor having a control electrode coupled to receive a first bias signal, the first transistor coupled between the first differential amplifier and the high potential source; a second transistor having a control electrode coupled to receive a second bias signal, the second transistor coupled between the second differential amplifier and the low potential source; a first clamp circuit coupled between the first input node and the first output node; and a second clamp circuit coupled between the second input node and the second output node. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A voltage controlled oscillator circuit connected between a high potential source and a low potential source, the circuit comprising:
a plurality of stages, each stage comprising; a first differential amplifier connected to first and second input nodes to receive first and second input signals, and connected to first and second output nodes for supplying first and second output signals; a second differential amplifier connected to the first and second input nodes to also receive the first and second input signals, and connected to first and second output nodes for also supplying the first and second output signals; a first transistor having a control electrode coupled to receive a first bias signal, the first transistor coupled between the first differential amplifier and the high potential source; a second transistor having a control electrode coupled to receive a second bias signal, the second transistor coupled between the second differential amplifier and the low potential source; a first clamp circuit coupled between the first input node and the first output node; a second clamp circuit coupled between the second input node and the second output node; and wherein the first and second output signals from each stage are coupled to provide as the next first and second input signals to the next stage. - View Dependent Claims (9, 10, 11)
Specification